Coded data generation or conversion – Digital code to digital code converters – Byte length changed
Patent
1990-02-20
1991-05-14
Pellinen, A. D.
Coded data generation or conversion
Digital code to digital code converters
Byte length changed
341100, 341101, H03M 900
Patent
active
050160117
ABSTRACT:
Conversion apparatus is used to convert digital data words to a digit-serial data format wherein digit bit-width is optimal for subsequent processing of the digital data words. Optimization is with regard to throughput efficiency, a measure of integrated circuit performance proportional to throughput rate of integrated circuitry and inversely proportional to the area of that integrated circuitry, comprising processing circuitry and attendant conversion circuitry.
REFERENCES:
patent: 3765013 (1973-10-01), Leibowitz
patent: 4023144 (1977-05-01), Koenig
patent: 4377806 (1983-03-01), Elliott et al.
patent: 4409587 (1983-10-01), Scott
patent: 4447804 (1984-05-01), Allen
patent: 4672362 (1987-06-01), Furukawa et al.
patent: 4728930 (1988-03-01), Grote et al.
patent: 4794627 (1988-12-01), Grimaldi
"Digital Circuit Optimization", C. E. Leiserson, F. M. Rose & J. B. Saxe, MIT Report (1982).
"Models for VLSI Circuits", F. M. Rose, MIT Master's Thesis (1982).
"Sehwa": A Program for Synthesis of Pipelines, N. Park & A. Parker, IEEE Proceedings of the 23rd Design Automation Conference (1986).
"The VLSI Design Automation Assistant: Prototype System", T. J. Kowalski et al., IEEE Proceedings of the 20th Design Automation Conference (1983).
"An Approach to the Implementation of Digital Filters" L. B. Jackson et al., IEEE Transactions on Audio Electronics, vol. AU-16, No. 3, pp. 413-421 (1968).
"A Bit-Serial VLSI Architectural Methodology for Signal Processing", R. F. Lyon, VLSI 81, Academic Press, 1981.
VLSI Signal Processing: A Bit-Serial Approach, P. Denyer & D. Renshaw, Addison Wesley Publishing Co., Inc., Reading, Mass. (1985) pp. 3-6 & 29-56.
"Digit Pipelined Arithmetic as Illustrated by the Paste-up System: A tutorial", M. J. Irwin & R. M. Owens, Computers, Apr. 1987, pp. 61-73.
"Custom Design of a VLSI PCM-FDM Transplexer . . . ", R. Jain et al., IEEE Journal of Solid-State Circuits, vol. SC-21, No. 1, Feb. 1986, pp. 73-85.
"A Bit-Serial Silicon Compiler", J. R. Jasica et al., Proceedings of the International Conf. on Computer-Aided Design, ICCAD085, Santa Clara, CA, pp. 91-93 (1985).
"Radix-4 Modules for High Performance Bit-Serial Computation", S. G. Smith & P. B. Denyer, IEEE Proceedings, vol. 134, Pt. E, No. 6, Nov. 1987, pp. 271-276.
Techniques to Increase the Computational Throughput of Bit-Serial Architectures, S. G. Smith, M. S. McGregor, P. B. Denyer, Proceedings of ICASSP 87, pp. 543-546. Apr. 1987.
Corbett Peter F.
Hartley Richard I.
Yassa Fathy F.
Davis Jr. James C.
General Electric Company
Hoff Marc S.
Limberg Allen L.
Pellinen A. D.
LandOfFree
Increased performance of digital integrated circuits by processi does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Increased performance of digital integrated circuits by processi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Increased performance of digital integrated circuits by processi will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1651605