Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-02-19
2000-07-18
Trinh, Michael
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438253, 438255, 438396, 438398, H01L 218242
Patent
active
060906553
ABSTRACT:
Disclosed is a three-dimensional integrated memory cell having a high interior volume and a method for constructing the same. The cell makes use of a highly conductive substrate material for the bottom electrode, allowing construction of a thin substrate without intolerable resistance. The substrate of the preferred embodiment, for example, comprises titanium silicide. The preferred method comprises conformal deposition of a thin polysilicon layer within a high aspect ratio container, followed by deposition of a suitable metal for silicidation with the polysilicon layer. The metal need not be conformal for this preferred method and may be deposited by sputter deposition. After silicidation, excess metal is selectively etched away to leave a conformal, thin yet highly conductive substrate material. The greater volume available due to this thinner substrate permits either scaling down of the cell dimension for more dense arrays with maintained capacitance per memory cell, or use of larger microstructures over the bottom electrode substrate, such as hemispherical grained silicon layers, for increased electrode surface area and greater capacitance.
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Lane Richard H.
Zahurak John K.
Micro)n Technology, Inc.
Thomas Toniae M.
Trinh Michael
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