Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-07-30
2001-07-17
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S289000, C438S291000
Reexamination Certificate
active
06261886
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to threshold voltage modulation in FET semiconductor devices.
2. Brief Description of the Prior Art
The threshold voltage, V
T
, of a field effect transistor (FET) depends upon the voltage on the substrate or body region (the region between the source region and the drain region). The threshold voltage can be changed by changing the body voltage. For an n-channel transistor, an increase in body voltage lowers (makes less positive or more negative) the threshold voltage. For a p-channel transistor, an increase in the body voltage raises (makes more negative or less positive) the threshold voltage, V
T
. Accordingly, for an n-channel transistor, when the gate voltage goes high, the capacitive coupling to the body region raises the body voltage and lowers the threshold voltage. This provides increased drive current. When the gate is turned off, the gate coupling raises the threshold voltage by lowering the body voltage, thereby providing decreased leakage current when the transistor is off. This capacitive coupling of the gate to the body is significant only when the conductive channel (inversion region) from the source region to the drain region is not formed. When the conductive channel is formed, it electrically isolates the gate from the body. Therefore, after the channel is formed, the advantage of the capacitive coupling of the gate to the body is no longer improved.
In the prior art, the edges of a transistor were sometimes doped more heavily to prevent leakage at the edge. The more heavily doped edge region would have a higher V
T
and thus the gate-to-body capacitive coupling would exist at the edge region for a greater range of gate voltage than at the channel region. However, the more heavily doped region would be made as small as practical, and a sidewall dielectric thicker than the gate oxide would generally be used. A sidewall insulator is required with mesa isolation. With shallow trench isolation (STI), the space between sidewalls is filled with dielectric. In the prior art, the sidewall insulator is typically several time the thickness of the gate oxide. Thus, the contribution of the highly doped edge region to the gate-to-body coupling would not be substantial.
Assuming, for example, an n-channel transistor, coupling of the gate to the body of the transistor causes dynamic V
T
modulation, thereby increasing V
T
when the transistor is off and decreasing V
T
when the transistor is on. However, direct coupling from the gate to a body contact results in gate current and diminished chip area. These problems have been attacked in the prior art by providing separate capacitors which are connected between the gate and the body of the transistor. This eliminates gate current but still diminishes chip area. Also, resistance in the connection of the capacitor to the body diminishes the effectiveness of the coupling. It is therefore desirable to increase the capacitive coupling between the gate and the body of a FET as well as to do so in a more economical, more effective and simpler procedure.
SUMMARY OF THE INVENTION
The above noted desires are readily accomplished in accordance with the present invention in a simple and economical manner.
Briefly, to provide an enhancement of on current and-a suppression of leakage current with voltage change on the gate of an FET, the capacitive coupling between the gate and the body of the FET is increased by providing a region under the gate, contiguous with the channel region, having a much higher threshold voltage than the channel region. This region may be adjacent to one or both edges of the channel region, going from source to drain. For silicon on insulator (SOI) transistors with a mesa structure, the high V
T
region may be adjacent to a mesa edge (referred to as a transistor sidewall). Here, higher V
T
means more positive (less negative) for n-channel and more negative (less positive) for p-channel. Alternatively, the high V
T
region may be anywhere along the width of the transistor and may be encompassed within the low V
T
region. Multiple high V
T
regions may be distributed within the channel region.
Coupling of the gate to the body is further increased by using a leaky gate dielectric. However, gate leakage through the gate oxide can be to the body region only when the channel is not formed. Thus, this method of influencing the body voltage is more effective in a high V
T
region. Having a thin gate dielectric also has well known benefits in drive current and reduced short channel effects. However, gate leakage to the source, drain or channel is generally not desirable. A structure with selectively thin (less than 20 nanometers) or leaky gate dielectric over the high V
T
region maximizes the beneficial influence of the gate coupling to the body while reducing total gate leakage. In the case of the leaky dielectric, the dielectric over the high V
T
region is leakier than the dielectric over the low V
T
region. This can be accomplished by, for example, growing a thin oxide, e.g. 15 nanometers, depositing a nitride and patterning and etching the nitride/oxide stack to expose the low V
T
regions. The gate oxide is then grown, the remaining nitride is stripped and the procedure progresses in standard manner. Although this arrangement is not the same as a direct contact to the body, the gate current influence on the body potential is beneficial.
The capacitive coupling of the gate to the body provides a floating body with some of the benefits of dynamic V
T
modulation. This capacitive coupling is reduced by the shielding of the gate from the body by the channel when the channel is formed. It has been suggested in the prior art to build a separate capacitor to capacitively couple the gate to the body. This extra capacitance can be built efficiently in accordance with the present invention by having extra doping in portions of the channel to raise the V
T
in those regions. Since the high V
T
region is adjacent to the channel region, there is minimal series resistance between the capacitive coupling to the gate and the body region at the channel. If this capacitance is provided at the edges of the transistor, this will have the extra benefit of suppressing any edge leakage. This can be accomplished in a self-aligned manner using what has been previously described for edge implant, but with a larger offset to provide area for the gate-to-body capacitance.
For example, a nitride is deposited over the pad oxide and patterned and etched for a moat (undersized). Then polysilicon sidewalls are added and the isolation, such as trench isolation or LOCOS, is formed. The polysilicon sidewalls are removed and a channel stop is implanted to form the capacitor area Standard processing of the transistor, including V
T
implants, follows. The described process forming and later removing sidewalls on the patterned moat masking layer has the advantage of self-alignment of the high V
T
regions to the transistor edge. High V
T
regions interior to the transistor edges can also be formed with the described process sequence by including relatively narrow spaces (less than twice the sidewall width) in the nitride pattern where the high V
T
regions are to be formed. Alternatively, the moat masking layer can be further patterned after formation of the isolation and prior to the high V
T
implant. Typically, the species implanted into the high V
T
region and the low V
T
region will be the same conductivity type. Other variations of process sequence that can be used to form selective high V
T
regions, such as the use of counter doping schemes, will become apparent to those skilled in the art. For wide transistors, it is desirable to have a plurality of high V
T
regions distributed across the width of the transistor. It is not necessary that a high V
T
region extend to either source/drain region.
The extra gate-to-body coupling is particularly attractive for DRAM word lines (W/L) to couple the body voltage low when the W/L shuts off. It would also couple high wh
Brady III Wade James
Chaudhuri Olik
Pham Hoai
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Increased gate to body coupling and application to DRAM and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Increased gate to body coupling and application to DRAM and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Increased gate to body coupling and application to DRAM and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2494677