Electrical computers and digital data processing systems: input/ – Input/output data processing – Concurrent input/output processing and data transfer
Reexamination Certificate
2002-01-09
2004-10-19
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Concurrent input/output processing and data transfer
C710S029000, C710S036000, C710S040000, C710S244000, C709S200000, C709S213000, C709S214000, C718S106000, C712S216000, C712S220000, C712S225000, C711S141000, C711S150000, C711S151000, C711S168000
Reexamination Certificate
active
06807586
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to computer data cache schemes, and more particularly to a method and apparatus for simultaneously processing a series of data writes from a standard peripheral computer interface device when having multiple data processors in a system utilizing non-uniform memory access.
2. Description of the Related Art
In computer system designs utilizing more than one processor operating simultaneously in a coordinated manner, data handling from peripheral component interface (PCI) devices is controlled in a fashion that provides only for single transactions to be processed at one time or in strict order, if multiple data output commands are received from one of the PCI devices in a system utilizing any number of such devices. In a multiprocessor system which uses non-uniform memory access where system memory may be distributed across multiple memory controllers in a single system this may limit performance.
A PCI device, such as a hard disk controller, may issue a write command. Any multiple processor address control system will send a “invalidate” indication of the data line to be written to all caching agents or processors. One method of handling such invalidate's in the past is that a controller waits to receive acknowledgments that the data invalidate has been received and then makes that data line available for writing. The controller then sends an invalidate of a flag line for that data line, which was just made available for write. In the prior art, many such controllers will wait to receive acknowledgments from all memory sources prior to proceeding and then will accept the data from the PCI device attempting to write to memory. After such a device writes to the memory management device, that device makes the flag line available. Usually, controllers found in the prior art post write commands only in the same order as the invalidate commands are issued on a particular PCI bus.
All of this has the effect of slowing down system speed and therefore performance, because of component latency and because the ability of the system to process multiple data lines while waiting for invalidate indicators from other system processors is not fully utilized.
SUMMARY OF THE INVENTION
A first aspect of this invention is a method for controlling the sequencing of data writes from peripheral devices in a multiprocessor computer system. The computer system includes groups of processors, with each processor group interconnected to the other processor groups. In the method, a first data write is issued by a peripheral device in the system, queued, and checked for completion. The sequence order of overlapping write data is tracked. Both the first and the second write data are processed substantially simultaneously using one or more of the memory systems, but the processed second write data is output only after completion of the first data write. By starting the processing of subsequent data writes before completing previous data writes, the method of the invention increases overall performance of the system.
Another aspect of this invention is found in a multiprocessor computer system, itself The system has two or more groups of one or more processors each. The system also has a peripheral device capable of initiating first and second data writes producing first and second write data, respectively, and a queue capable of sequentially ordering the data writes. A completion indicator determines completion of the first data write, and a sequencer tracks overlapping of the write data, both in response at least in part to the write data. The system includes storage for the first and second write data, and output for the first and second write data which responds at least in part to the sequencer and the completion indicator. The storage for the second write data is capable of accepting the second write data before completion of the first data write, but the output for the second write data is capable of outputting the second write data only after completion of the first data write.
Other features and advantages of this invention will become apparent from the following detailed description of the presently preferred embodiment of the invention, taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5740398 (1998-04-01), Quattromani et al.
patent: 5905998 (1999-05-01), Ebrahim et al.
patent: 5926645 (1999-07-01), Williamson
patent: 6108721 (2000-08-01), Bryg et al.
patent: 6269433 (2001-07-01), Jones et al.
patent: 6421775 (2002-07-01), Brock et al.
patent: 6636933 (2003-10-01), MacLellan et al.
patent: 2003/0023782 (2003-01-01), Arimilli et al.
Berg Thomas B.
Beyer Dale A.
Moga Adrian C.
Abdy Raissinia
Gaffin Jeffrey
Law Offices of Michael Dryja
Nguyen Tanh Q
LandOfFree
Increased computer peripheral throughput by using data... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Increased computer peripheral throughput by using data..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Increased computer peripheral throughput by using data... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3300185