In-situ SiON deposition/bake/TEOS deposition process for reducti

Details In-situ SiON deposition/bake/TEOS deposition process for reducti In-situ SiON deposition/bake/TEOS deposition process for reducti

1998-11-25

2000-09-26

Smith, Matthew

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

438786, 438787, 438624, 438339, 438595, H01L 2131

Patent

active

061242179

ABSTRACT:
An interlevel dielectric including a tetraethyl orthosilicate (TEOS) oxide and a silicon oxynitride (SiON) etch stop layer is formed for use in integrated circuit fabrication. A SiON layer is deposited onto a semiconductor substrate which may include transistors and/or interconnect levels. The SiON layer is heated before deposition of the TEOS layer. Heating of the SiON layer greatly reduces the number of defects formed during the TEOS deposition. A highly conformal, high-quality interlevel dielectric is thereby formed.

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