Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-09-28
2004-09-28
Vinh, Lan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S712000, C438S720000
Reexamination Certificate
active
06797633
ABSTRACT:
FIELD OF THE INVENTION
The invention is generally related to the field of forming interconnect layers in a semiconductor device and more specifically to patterning low-k dielectric films.
BACKGROUND OF THE INVENTION
As the density of semiconductor devices increases and the size of circuit elements becomes smaller to achieve better performance, the resistance capacitance (RC) delay time in back-end-of-line (BEOL) increases and dominates the circuit performance. To reduce the RC delay time at BEOL, the demands on interconnect layers for connecting the semiconductor devices to each other also increase. Therefore, there is a desire to switch from the traditional aluminum metal interconnects to copper interconnects and from traditional silicon-dioxide-based dielectrics to low-k dielectrics, such as organo-silicate glass (OSG). Semiconductor fabrication processes for working with the copper interconnects and newer low-k dielectrics are still needed.
As compared to the traditional subtractive plasma dry etching of aluminum, suitable copper etches for a semiconductor fabrication environment are not readily available. To overcome the copper etch problem, damascene processes have been developed. In a damascene process, the IMD (intra-metal dielectric) is formed first. The IMD is then patterned and etched to form trenches for the interconnect lines. If connection vias have not already been formed, a dual damascene process may be used. In a via-first dual damascene process, an ILD (interlevel dielectric) is deposited first, followed by an IMD deposition. An IMD etch-stop layer, such as SiN, can be optionally used in between IMD and ILD. A via is patterned and etched through the IMD and ILD for connection to lower interconnect levels. Then a trench is patterned and etched in the IMD. A barrier layer and a copper seed layer are then deposited over the structure. The barrier layer is typically tantalum nitride or some other binary transition metal nitride. The copper layer is electrochemically deposited (ECD) using the seed layer over the entire structure. The copper is then chemically-mechanically polished (CMP'd) to remove the copper from over the IMD, leaving copper interconnect lines and vias. A metal etch is thereby avoided.
When low-k dielectrics such as OSG are used for the IMD and ILD, a problem known as resist poisoning occurs. Resist poisoning occurs during a patterning step such as via pattern or trench pattern. It is a result of the interaction between a DUV (deep ultra-violet) resist and low-k films. Resist poisoning causes poor resist sidewall profiles, resist scumming, large CD variations, and requires a large resist exposure dose. Furthermore, the required resist exposure dose to achieve the target CD becomes too high and varies with film aging. A process to reduce or eliminate resist poisoning in low-k dielectrics is therefore desired.
SUMMARY OF THE INVENTION
The invention is an in-situ plasma treatment for low-k films that improves patterning. After via etch, the wafer with a low-k film is treated with a plasma, such as an O
2
plasma, to eliminate or significantly reduce resist poisoning. The plasma treatment may be performed in the same chamber or a separate chamber if the transfer is performed under vacuum. After plasma treatment, the trench patterning is performed.
An advantage of the invention is providing a treatment to reduce or eliminate resist poisoning of low-k dielectric films.
This and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings.
REFERENCES:
patent: 6042999 (2000-03-01), Lin et al.
patent: 6166439 (2000-12-01), Cox
patent: 6232237 (2001-05-01), Tamaoka et al.
patent: 6316354 (2001-11-01), Hu
patent: 6342448 (2002-01-01), Lin et al.
patent: 6350701 (2002-02-01), Yamazaki
patent: 6380096 (2002-04-01), Hung et al.
patent: 6455431 (2002-09-01), Hsieh et al.
Jiang Ping
Kraft Robert
Newton Kenneth J.
Rogers Daty M.
Brady III W. James
Garner Jacqueline J.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Vinh Lan
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