Imprint compensation circuit for use in ferroelectric semiconduc

Static information storage and retrieval – Systems using particular element – Ferroelectric

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365149, G11C 1122

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active

058353992

ABSTRACT:
A semiconductor memory device having a unit memory cell consisting of, a ferroelectric capacitor having a first and second electrodes, and an access transistor connected to the first electrode of the capacitor and to the bit line, is disclosed. An imprint compensation circuit for applying a predetermined voltage to the first electrode through the write path of the memory device, or for applying a signal in the form of pulse to the second electrode, where data access of the memory device is prohibited, in order to imprint the ferroelectric capacitor in first and second directions from the reference point, creating a normal polarization characteristic.

REFERENCES:
patent: 5592410 (1997-01-01), Verhaeghe et al.
patent: 5600587 (1997-02-01), Koike

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