Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2011-08-02
2011-08-02
Garber, Charles D (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
Reexamination Certificate
active
07989337
ABSTRACT:
A method and structure are provided for implementing vertical airgap structures between chip metal layers. A first metal layer is formed. A first layer of silicon dioxide dielectric is deposited onto the first metal layer. A vertical air gap is etched from the first layer of silicon dioxide dielectric above the first metal layer. A second layer of silicon dioxide dielectric is deposited and the vertical air gap is sealed. A next trace layer is etched from the second layer of silicon dioxide dielectric and a via opening is etched from the second and first layers of silicon dioxide dielectric. Then metal is deposited into the next trace layer and metal is deposited into the via opening.
REFERENCES:
patent: 5461003 (1995-10-01), Havemann et al.
patent: 7056822 (2006-06-01), Zhao
patent: 7407826 (2008-08-01), Jafri et al.
Aguado Granados Axel
Fox Benjamin Aaron
Gibbs Nathaniel James
Maki Andrew Benson
Timpane Trevor Joseph
Garber Charles D
International Business Machines - Corporation
Pennington Joan
Stevenson Andre′ C
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