Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – On insulating substrate or layer
Reexamination Certificate
2000-01-05
2002-08-06
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
On insulating substrate or layer
C438S233000, C438S407000, C438S423000, C438S967000
Reexamination Certificate
active
06429099
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method to implement body contacts of transistors on semiconductor-on-insulator, especially silicon-on-insulator (SOI), semiconductor technology.
DESCRIPTION OF THE RELATED ART
Metal Oxide Semiconductor Field Effect Transistor (MOSFET) scaling on bulk silicon has been the primary focus of the semiconductor and microelectronic industry for achieving Complementary Metal Oxide Semiconductor (CMOS) chip performance and density objectives. The shrinking of MOSFET dimensions for high density, low power and enhanced performance requires reduced power supply voltages. Because power consumption is a function of capacitance, voltage, and transition frequency, the focus has been on reducing both the capacitance and the voltage as the switching frequency increases. As a result, dielectric thickness and channel length are scaled with power supply voltage. Power supply reduction continues to be the trend for future low voltage CMOS, however, transistor performance is severely impacted by both junction capacitance and the MOSFET body effect at lower voltages. As technologies scale below 0.25 &mgr;m channel lengths, to 0.15 &mgr;m and 0.1 &mgr;m and shorter, short channel effects control, gate resistance, channel profiling and other barriers become an issue for advanced CMOS technologies. While significant success has been achieved with successive scaling of bulk CMOS technology, the manufacturing control issues and power consumption will become increasingly difficult.
Silicon-on-insulator (SOI) technology is an enhanced silicon technology in which an insulating layer is situated above the bulk CMOS layer. SOI transistors are built in a thin layer of silicon on top of a buried insulator, typically silicon oxide or glass, with bulk silicon below the buried insulator. Using SOI technology eliminates many of the concerns and obstacles of bulk silicon CMOS at low power supply voltages. SOI has significant advantages over bulk CMOS technology and will achieve the scaling objectives of low power and high switching frequency for future technologies. SOI provides low power consumption, low leakage current, low capacitance diode structures, good sub-threshold I/V (current/voltage) characteristics, a low soft error rate from both alpha particles and cosmic rays, good SRAM access times, to name only some of the technology benefits offered by SOI. Because of these advantages, SOI technology is especially useful in portable and wireless applications.
SOI technology allows for the mapping of standard advanced technologies into an SOI technology without significant modifications. SOI process techniques include epitaxial lateral overgrowth, lateral solid-phase epitaxy and full isolation by porous oxidized silicon. SOI networks can be constructed using the semiconductor process of techniques of separation by implanted oxygen and wafer-bonding and etch-back because they achieve low defect density, thin film control, good minority carrier lifetimes and good channel mobility characteristics. Structural features are defined by shallow-trench isolation. Shallow trench isolation eliminates planarity concerns and multidimensional oxidation effects, thereby allowing technology migration and scaling to sub-0.25 &mgr;m technologies.
FIGS. 1 and 2
illustrate a conventional SOI transistor.
FIG. 1
illustrates a cross section through the width of a traditional SOI transistor. The SOI transistor has a polysilicon gate, a gate oxide over a thin silicon layer with isolation oxide, over a buried oxide, over the bulk silicon substrate. Performance of SOI transistors is increased because reduced diffusion capacitance and floating body properties result in lower transistor threshold voltages. Because the voltage of the floating body can vary over time, the threshold voltage also varies. The floating body effects were considered beneficial because of the increased speed at which a transistor can switch. Performance, however, cannot be predicted using transistors in which the bodies are allowed to float. Floating body transistors, moreover, are extremely sensitive to nonperfect input voltage on the gates and to noise. Because of “history effects”, moreover, floating body transistors are difficult to match, in part because of this sensitivity described above and in part because the voltage on the floating body is dependent upon previous cycles and the time durations of the cyclic input. For instance, a high signal immediately after two or three other high signals might be output too fast in order to synchronize with other signals. Similarly, a low signal immediately after two or three high signals might be too slow.
In situations and circuits in which the effects associated with floating bodies are undesirable, there are known structures that can be used to connect the body of the SOI transistor to a known voltage. However, the known structures add much capacitance to the device, particularly gate capacitance, thus degrading the performance of these transistors so that is worse than a traditional bulk transistor.
FIG. 2
illustrates a traditional body contact of a SOI transistor. Increased polysilicon area is needed to fabricate the traditional body contact. The increased polysilicon results in a large increase in capacitance of the SOI transistor, thus degrading performance.
In the past, electrically connecting the transistor body to a fixed voltage typically increased the size of SOI devices and as such it was considered undesirable. Other attempts have been made to allow body contact with non-uniformly doped channel regions, however, the use of non-uniformly doped channel regions may cause the devices' threshold voltage to change. Other techniques to contact the body of SOI transistors to a voltage are complex and involve multiple process steps using multiple films. These techniques, however, may exacerbate the problem because transistors bodies have high electrical resistance which generates heat. When switching transistors at high frequencies on the order of gigahertz, or once every tens, rather than hundreds of picoseconds, the resistance resulting from large contacts to the transistor bodies causes delay in the transitions because of the resistance-capacitive delay and it is difficult to keep the body at a fixed voltage, especially at ground voltage.
Existing SOI transistors with body contacts require significantly more physical area than their counterpart transistors not having body contacts. Conventional body contacts involving a large “T” or “L” shaped gate where the horizontal layout segment(s) separate the active body region from the body contact region increase the total transistor physical area on the order of fifty percent. Given the same input signal on a non-body contacted transistor and depending on transistor width, the added gate area required by body contacts for SOI transistors typically doubles the total gate capacitance requiring twice the input rise time. The increased area and/or delay penalty render the body-contacted SOI transistors less desirable.
And yet another undesirable result of traditional body contacts in a SOI transistor is a large resistance between the electrical connection between the desired power grid, typically ground for a NFET body, and the actual body itself. Because the connection is through thin lightly doped semiconductor levels, resistances on the order of tens of thousands of ohms are typical.
There is thus a need in the semiconductor-on-insulator industry for a body contact that can operate at high frequencies but does not have high capacitance nor high resistance,
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide a method and semiconductor structure fabricated using the method for implementing body contacts for semiconductor-on-insulator transistors. Other important objects of the present invention are to provide such a method and semiconductor structure for implementing body contacts for silicon-on-insulator (SOI) transistors without substantial negative effect and that overcome m
Christensen Todd Alan
Sheets, II John Edward
Brophy Jamie L.
Jr. Carl Whitehead
Ojanen Karuna
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