Implementation of an LRU and MRU algorithm in a partitioned...

Details Implementation of an LRU and MRU algorithm in a partitioned... Implementation of an LRU and MRU algorithm in a partitioned...

2005-08-16

2005-08-16

Nguyen, Hiep T. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S128000

Reexamination Certificate

active

06931493

ABSTRACT:
The present invention provides for determining an MRU or LRU way of a partitioned cache. The partitioned cache has a plurality of ways. There are a plurality of partitions, each partition comprising at least one way. An updater is employable to update a logic table as a function of an access of a way. Partition comparison logic is employable to determine whether two ways are members of the same partition, and to allow the comparison of the ways correlating to a first matrix indices and a second matrix indices. An intersection generator is employable to create an intersection box of the memory table as a function of a first and second matrix indices. Access order logic is employable to combine the output of the intersection generator, thereby determining which way is the most or least recently used way.

REFERENCES:
patent: 6782457 (2004-08-01), Hill et al.
patent: 2003/0159003 (2003-08-01), Gaskins et al.

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