Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-04-20
2003-12-09
Fahmy, Wael (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S298000, C438S450000, C438S451000, C438S982000, C257SE21557
Reexamination Certificate
active
06660595
ABSTRACT:
FIELD OF THE INVENTION
The instant invention pertains to semiconductor device fabrication and processing and more specifically to a method of implanting dopant into one region of silicon material while blocking the implantation in another region.
BACKGROUND OF THE INVENTION
Implantation of dopants into the semiconductor substrate (or epitaxial silicon layer which overlies the semiconductor substrate) is important in semiconductor device fabrication. Many different implantation steps need to be performed so as to: dope the polycrystalline silicon (“poly” or “polysilicon”) gate structure, form drain extensions, form pockets, form source and drain regions, form isolation structures, and to increase or decrease the conductivity of semiconductor structures. A problem with all of these implantation steps is that they may require separate masks (see mask
106
of
FIGS. 1
a
and
1
b
) so as to block the implantation of dopants from one region while exposing other regions (see open region
108
of
FIGS. 1
a
and
1
b
) to the implantation of dopants. Formation of these masks is very expensive and can be quite difficult to implement due to the ever-shrinking feature sizes and the difficulties associated with present limitations on photolithography. Some relief from these problems can be achieved by using existing structures to act as masks for the implantation of dopants. For example, the gate structure
102
(not including a sidewall spacer) and the isolation structures can be used to define the region where the drain extensions are formed. In addition, the isolation structures and the gate structure, which includes a sidewall spacer, can be used to define the region in which dopants are implanted to form the source and drain regions. However, this self-alignment methodology can not solve all of the problems related to precisely implanting dopants into these semiconductor structures.
Typically, dopants are implanted into the semiconductor structure normal to the semiconductor wafer (hereinafter referred to as an angle, phi, which would be equal to zero degrees if it were normal to the wafer). However, implanting normal to the wafer can be problematic. Some of the problems associated with implanting normal to the wafer include: dopant channeling and inability to position dopants sufficiently laterally underneath a masked region. In an effort to alleviate these problems, semiconductor device manufacturers have started to implant dopants at an angle from the normal to the wafer. In order to properly implant into the areas which are to be doped, semiconductor device manufacturers have altered their implantation methodology so as to implant a quarter of the dopants with angle phi being non-zero at an angle from 7-50 degrees with the dopants striking the wafer normal to the gate structure (hereinafter referred to as angle theta with theta being at zero degrees when normal to the gate structure)[see angle
110
of
FIG. 1
a
]. The other three-quarters of the dopants being implanted when theta is at 90 degrees (angle
116
of
FIG. 1
a
), 180 degrees (angle
114
of
FIG. 1
a
) and 270 degrees (angle
112
of
FIG. 1
a
), respectively.
While this angled implantation solves some of the problems associated with implantation normal to the substrate, it does not lessen the number of masking steps required to form all of the different doped structures. Hence, there is a need for a methodology which will result in one structure being implanted with a dopant while another structure remains free of those dopants without having to use multiple masking steps.
SUMMARY OF THE INVENTION
The invention is a method of fabricating an integrated circuit that uses a shadowing effect to block dopants from an exposed area. A layer, such as a masking layer, is formed exposing two regions of the semiconductor body. The width of the second region is less than the width of the first region. A dopant is implanted at an angle, phi, from normal using the layer and rotating the semiconductor body at off angles, theta, so as to implant the dopant into the first exposed region but not substantially into the second exposed region.
In one embodiment, the invention is used to form pocket regions in one transistor but not another. A masking layer has two openings that expose two transistor areas. The width of the second opening is adjusted such that the angled implant is substantially blocked from the second transistor. The angled implant forms pocket regions in the first transistors. The same masking layer may then be used to implant source and drain extension regions in both the first and second transistors.
An advantage of the invention is providing a method of fabricating an integrated circuit using a reduced number of masking levels.
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patent: 6159790 (2000-12-01), Gonzalez et al.
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Brady III W. James
Fahmy Wael
Garner Jacqueline J.
Rao Shrinivas H.
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