Impedance control circuit

Details Impedance control circuit Impedance control circuit

2001-06-01

2003-06-03

Lee, Michael G. (Department: 2876)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S027000, C326S082000, C326S086000, C326S021000

Reexamination Certificate

active

06573746

ABSTRACT:

BACKGROUND
1. Technical Field
The present invention relates generally to an impedance control circuit and, more particularly, to an impedance control circuit that reduces the variance of an external impedance that is generated from an external resistor to match to an internal impedance.
2. Description of Related Art
Recently, the use of various “on-chip” termination techniques have be employed for high-speed data transmission in digital circuit designs. In one method, an on-chip parallel termination is utilized together with series termination. An advantage of parallel termination is that good signal integrity is maintained, although the swing level of the signal may be lowered due to minor dc power dissipation in the termination resistor. An advantage of series termination is that the termination resistor consumes less power than all other resistive termination techniques. When data is transmitted through a transmission line, if an output driver (Dout) and a receiver respectively operate as a source termination and parallel termination respectively, data is sent at a reduced swing level, but at the full swing of a signal.
It is preferable that the output driver and on-chip termination comprise a resistor. But since the output driver and on-chip driver are located in the chip, it is difficult to perform termination if a characteristic impedance of the transmission line lies in another environment. Thus, it is preferable to construct a circuit in which a desired impedance value can be programmable and set to the characteristic impedance of the transmission line.
In this regard, a programmable impedance control circuit may be employed for sensing the characteristic impedance of the transmission line and transmitting control signals indicative of the sensed impedance to adjust the impedance of the output driver and on-chip termination. The programmable impedance control circuit operates to substantially match the impedance to the value of a resistor that the user connects externally. Furthermore, the programmable impedance control circuit operates to match an internal impedance to an external impedance by actively updating digital codes based on changes in voltage and temperature (referred to as “VT change”).
One method that is used to construct the aforementioned programmable impedance control circuit is for a user to connect a resistor to one side of a chip, wherein the resistor has an impedance value that is substantially identical to the external impedance. If the external resistor is connected to ground outside, the relevant impedance may be generated at the top portion of the chip. If the impedance is generated using a digital code method, the impedance may have a quantization error. When the impedance having a quantization error is matched to the impedance of a down driver, a quantization error occurring at the down driver makes the variance of the impedance of the down driver even greater in addition to the quantization error at the top of the chip.
The above-described problems associated with conventional impedance control circuits will be explained with reference to
FIG. 1
, which illustrates a structure of a conventional impedance control circuit. To generate an impedance that is substantially identical to an external resistor RQ, a method is used to sense when the external impedance becomes identical to an internal impedance by comparing a reference voltage equal to {fraction (1/2 )} of the voltage VDDQ (where VDDQ indicates high-speed transceiver logic voltage) with, e.g., a pad voltage that is established by RQ and a MOS Array
1
. The impedance control circuit shown in
FIG. 1
receives information regarding the impedance of the external resistor RQ. In the circuit, an internal impedance is using digital codes to change the impedance of the MOS array
1
by changing the number of enabled transistors that form the MOS array
1
. Errors may be introduced by this circuit because these transistors of the MOS array operated in a linear region and are, thus, sensitive to VDDQ noise. Furthermore, the use of digital codes can result in a quantization error. A sensed impedance value having such errors is used to generate the impedance of a down driver, thereby making the variance even greater.
FIG. 2
illustrates another conventional impedance control circuit as disclosed in U.S. Pat. No. 5,606,275, entitled “Buffer Circuit Having Variable Output Impedance.” With this circuit, the impedance is separately generated by an up driver and down driver. The output buffer circuit
20
has an output impedance that is adjusted based on the resistance of an external resistor
32
. An NMOS transistor is used as a current source to provide resistant to VDD noise, and the bulk voltage is set at ground potential to place the operational region of a transistor into a saturation region. However, when the high-speed data transmission and high-integration of the chip reduces voltage of the chip, it is difficult to turn the operational region of the transistor into the saturation region with the bulk voltage of the NMOS transistor set at ground because the saturation region is so small. Furthermore, the circuit implements a complex process. Indeed, after the current source generates a current value that corresponds to the external resistor, the impedance of the down-driver is generated based on the generated current value and the current is duplicated to generate the impedance of the up-driver. Consequently, this process is complicated that it can be subject to errors that result in variance in the impedance.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an impedance control circuit that reduces errors in generating an internal impedance relating to an external resistance.
It is another object of the present invention to provide an impedance control circuit that can reduce error and effectively respond thereto even when the voltage of a chip decreases due to high-speed data transmission.
In one aspect of the present invention, an impedance control circuit comprises: an external resistor for establishing a first reference voltage; a comparator for comparing the first reference voltage with a second reference voltage and outputting an impedance corresponding to the result of the comparison; and a PMOS current source connected to a constant-voltage source and to the output of the comparator, wherein the PMOS current source generates a current that corresponds to the impedance.
In another aspect, the impedance control circuit further comprises a current mirror to duplicate the current of PMOS current source and transmit the current to an up and down driver. In one embodiment, the current mirror of the impedance control circuit is constructed using a PMOS and NMOS transistor.
In yet another aspect of the present invention, the impedance control circuit comprises: a pull-down circuit for receiving the current generated by the PMOS transistor of the current mirror and digitally coding the current relevant to the impedance; and a pull-up circuit for receiving the current generated by the NMOS transistor of the current mirror and digitally coding the current relevant to the impedance.
In one embodiment, the pull-down circuit comprises a second PMOS current source, connected to a constant-voltage source, for receiving current from the PMOS transistor of the current mirror; an NMOS detector connected to ground and to the second PMOS current source; a second comparator for comparing a third reference voltage with a fourth reference voltage established by the combination of the second PMOS current source and the NMOS detector and outputting an impedance corresponding to the comparison; and a first encoder for digitally coding the impedance output from the second comparator and outputting an impedance code to the down-driver. In addition, the pull-up circuit comprises: a NMOS current source, connected to ground, for receiving current from the NMOS transistor of the current mirror; a PMOS detector connected to a constant-voltage source and to the NMOS current source; a third

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