Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-10-10
2001-09-04
Lebentritt, Michael (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000, C438S789000
Reexamination Certificate
active
06284644
ABSTRACT:
BACKGROUND OF THE INVENTION
Fluorinated silica glass (FSG) is employed as a low dielectric constant (low-k) material for intermetal dielectric (IMD) layers for semiconductor technology of 0.18 &mgr;m and beyond (i.e. smaller sizes). However, complications in process integration may arise including:
(1) metal (e.g. Al) can be attacked by F-species leading to the formation of metal fluoride (e.g. AlF
3
);
(2) good planarity by chemical mechanical polishing (CMP) is usually achieved by polishing more FSG thus increasing the cost of the, already, expensive materials; and
(3) the current scheme (method) employing SRO as a capping layer is unstable and is causing the problem of depth of focus (DOF) during patterning of the via mask resulting in poor critical dimension (CD) uniformity.
The above problems can escalate to bad process integration at back-end-of-line (BEOL) processes.
U.S. Pat. No. 6,008,120 to Lee describes a metal line, liner layer, FSG and an oxide layer, and a via.
U.S. Pat. No. 6,028,013 to Annapragada et al. describes a metal, FSG and (PECVD) oxide layer.
U.S. Pat. No. 5,763,010 to Guo et al. describes a method of stabilizing halogen-doped silicon oxide film to reduce halogen atoms migrating from the film during subsequent processing steps. A halogen-doped film is deposited over a substrate and is then subjected to a degassing step by briefly heating the film to between about 300 and 550° C. before deposition of a diffusion barrier layer. The heat treatment is thought to remove loosely bonded halogen atoms from the halogen-doped film. In a preferred embodiment, the halogen-doped silicon oxide film is FSG film that is subjected to a degassing treatment for between about 35 and 50 seconds.
U.S. Pat. No. 5,244,535 to Ohtsuka et al. describes a method of manufacturing a semiconductor device including a nitrogen-containing plasma treatment of contact holes. The contact holes are etched through an insulation layer (for example SiO
2
) with a fluorine-based gaseous plasma, and the contact holes are then immediately flooded with the nitrogen-containing plasma that inhibits formation of reaction products on the exposed portion of the contact holes.
U.S. Pat. No. 5,643,407 to Chang describes a method of forming via openings through an intermetal dielectric (IMD) layer (comprised of spin-on-glass (SOG) sandwiched between two layers of silicon oxide (SiO
2
)) to an underlying patterned first metal layer. A vacuum bake is used to remove moisture from the exposed SOG layer within the via opening and then a nitrogen plasma treatment converts the SOG layer from an organic to an inorganic material. The inorganic SOG layer material has less moisture absorption, and suppresses outgassing from the rest of the organic SOG layer to prevent poisoned via metallurgy.
U.S. Pat. No. 5,578,524 to Fukase et al. describes an intermediate insulation layer between a wiring of gate electrodes and a wiring formed in an upper layer that includes a first interlayer insulation layer, a silicon rich oxide layer stacked on the first interlayer insulation layer and containing excessive silicon atoms. A second interlayer insulation layer is stacked over the silicon rich oxide layer. A selective dry etching process is used to etch the insulation layers to simultaneously form a self-aligned type contact hole on the diffusion layer position at the gap between oppositely arranged gate electrodes and a contact hole on the wiring of the predetermined gate electrode.
U.S. Pat. No. 6,035,803 to Robles et al. describes a method and apparatus for controlling the deposition of a fluorinated carbon film. A carbon-based dielectric film is deposited on a substrate in a processing chamber by first flowing a process gas including a gaseous source of carbon (e.g. CH
4
) and a gaseous source of halogen (e.g. C
4
F
8
). A plasma is then formed from the process gas by applying a first and then second RF power component for a period of time to deposit a halogen-doped carbon-based layer.
U.S. Pat. No. 6,054,379 to Yau et al. describes a method and apparatus for depositing a low dielectric constant film by reaction of an organo silane compound and an oxidizing gas.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of forming a via opening in an IMD layer including a fluorinated silica glass (FSG) dielectric sublayer while preventing outgassing from the FSG dielectric sublayer.
Another object of the present invention is to provide a method of forming a via opening within an IMD layer including a first treated FSG dielectric sublayer then subjecting the via opening to a second treatment to treat the exposed sidewalls of the first treated FSG dielectric sublayer while depleting fluorine species on the exposed surface of the fluorinated silica glass dielectric layer within the via opening to prevent outgassing from the FSG dielectric sublayer.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a semiconductor structure having a metal structure formed thereover is provided. A liner layer is formed over the semiconductor structure, covering the metal structure. A fluorinated silica glass dielectric layer is formed over the liner layer. The fluorinated silica glass dielectric layer having an exposed upper surface. The fluorinated silica glass dielectric layer is treated with a first nitrogen gas/plasma treatment to form a fluorine depleted upper capping layer from the exposed surface of the fluorinated silica glass dielectric layer. A TEOS oxide layer is formed over the upper capping layer. The TEOS oxide layer is planarized to form a planarized TEOS oxide layer. The planarized TEOS oxide layer, the upper capping layer, the treated fluorinated silica glass dielectric layer, and the liner layer are patterned to form a via hole therethrough, exposing a portion of the metal structure and exposing sidewalls of the patterned treated fluorinated silica glass dielectric layer within the via opening. At least the exposed sidewalls of the patterned treated fluorinated silicon glass dielectric layer within the via opening is treated with a second nitrogen gas/plasma treatment to form a fluorine depleted sidewall capping layer from the exposed sidewalls of the patterned treated fluorinated silicon glass dielectric layer, wherein the upper and sidewall capping layers prevent the outgassing from the patterned fluorinated silica glass dielectric layer. A metal interconnect is formed within the via opening.
REFERENCES:
patent: 5244535 (1993-09-01), Ohtsuka et al.
patent: 5571572 (1996-11-01), Sandhu et al.
patent: 5578524 (1996-11-01), Fukase et al.
patent: 5643407 (1997-07-01), Chang
patent: 5763010 (1998-06-01), Guo et al.
patent: 6008120 (1999-12-01), Lee
patent: 6028013 (2000-02-01), Annapragada et al.
patent: 6035803 (2000-03-01), Robles et al.
patent: 6054379 (2000-04-01), Yau et al.
patent: 6072227 (2000-06-01), Yau et al.
patent: 6130157 (2000-10-01), Liu et al.
patent: 6136680 (2000-10-01), Lai et al.
patent: 6153512 (2000-11-01), Chang et al.
Aug Arthur Khoon Siah
Chen Feng
Li Qiong
Chartered Semiconductor Manufacturing Ltd.
Lebentritt Michael
Pike Rosemary L. S.
Saile George O.
Stanton Stephen G.
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