Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1998-02-19
2001-01-09
Ballato, Josie (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
Reexamination Certificate
active
06172512
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the testing of VLSI circuits, and in particular to a system and method for determining the source of circuit failures that are associated with changes in operating conditions.
BACKGROUND OF THE INVENTION
Until recently, most fails in CMOS integrated circuits involved behavior that appeared as soon as power was applied. Faulty gates that were supposed to draw no current, for example, drew significant currents. Failure analysis consisted of the physical identification of these gates. Today, there are many more subtle failures. For example, circuits often show good static and low frequency behavior, but produce errors when operated at high frequencies. Other problems stem from proper functionality at some temperatures, and not others, etc. The fails can be as subtle as errors in calculations which occur only when the operating frequency of the chip is above some level. In fact, the performance of modern integrated circuits is verified by operating them at a particular speed, and checking to see if the correct output is produced after a particular set of operations. The process is iterated until a speed is reached where errors appear. The chip is then sold as one that works properly at the highest speed where no errors were detected.
The process of identifying the specific devices or circuits which limit the high speed performance of a chip is commercially critical since the value of the part increases rapidly with increasing computational power. The computational power of a chip is determined by its design and by the frequency at which it operates. However, identification of the devices within a circuit that limit the high frequency performance is difficult today. This is because logic circuits can now involve more than 10 million gates, and the instructions that produce a detectable error in the operation of the microprocessor can involve tens of thousands of cycles of the microprocessor. The detected error can be due to a problem in a single gate during one cycle. Thus, if there are 10 million gates, and the test involves 10 thousand processor cycles, there are potentially 100 billion switching events that must be checked. Existing techniques that involve the serial measurement of the voltage waveforms for every node would be extremely time consuming under such conditions and therefore lack practicality for testing modern integrated circuits.
In the past, dynamic fault imaging has been used in the effort to detect the source of errors in VLSI circuits. Dynamic fault imaging involves IC testers running extensive test patterns and at each test vector, the generation and storage of an e-beam image showing all logic states on a chip. In the past, dynamic fault imaging required hundreds of test vectors to perform such a test; currently, tens of thousands or more are needed due to increased design complexity. This process was done for a good chip and for a failing chip and then digital subtraction of the two data sets was performed to obtain an image of the fault. This method is not widely practiced on modern integrated circuits due to device complexity, multiple metal levels, complex bussing and flip chip packaging, all of which limit the ability of an e-beam based tester to obtain an image in a reasonable amount of time, or at all.
Commonly owned and copending U.S. Pat. No. 5,940,545, entitled NONINVASIVE OPTICAL METHOD FOR MEASURING INTERNAL SWITCHING AND OTHER DYNAMIC PARAMETERS OF CMOS CIRCUITS, incorporated herein by reference, describes a technique referred to herein as picosecond imaging circuit analysis (PICA) which is used to acquire data representing the switching of CMOS gates in an integrated circuit. Every switching event produces a pulse of light which can be captured by an optical detector. In contrast to the previously described e-beam techniques where data must be obtained individually from each net of the circuit, the PICA technique provides a means for obtaining, in a single measurement, the switching waveforms of all of the gates in an integrated circuit. The ability to obtain in a single measurement full switching information from a complex integrated circuit means that the solution for identifying a defect is no longer limited by the length of time required to acquire the relevant data, but rather is limited by the ability to identify a single event in a field of hundreds of billions of switching transitions.
SUMMARY OF THE INVENTION
This invention provides simple means for using picosecond imaging circuit analysis data and digital image processing to identify the source of these faults.
In accordance with the invention, a system and method are provided for detecting the source of faulty operation given an integrated circuit that operates properly under a first set of operating conditions and improperly under a second set of operating conditions, comprising: in a first test operation, applying a first input to the integrated circuit under a first set of conditions which result in proper circuit operation; obtaining a first image of light emissions from the circuit while the circuit is processing the first input, the light emissions originating from switching operations of devices in the circuit; storing the image as x,y,t data, where x and y indicate a location in the circuit, and t indicates a time increment during the processing of the test input; in a second test operation, applying a second input to the integrated circuit, the second input being functionally identical to the first input, but under a second set of external conditions which result in improper circuit operation; obtaining a second image of light emissions from the circuit while the circuit is processing the second input under the second set of conditions; and comparing the first and second images to determine the source of the faulty operation of the circuit.
In accordance with a second embodiment of the invention, a system and method are provided for detecting the source of faulty operation of an integrated circuit where proper operation of the circuit under some conditions is not required as a reference, but where a properly operating, functionally equivalent circuit is available to generate a “golden image.” This comprises: in a first test operation, applying a first input to a properly operating integrated circuit under a first set of conditions; obtaining a first image of light emissions from the first circuit while the circuit is processing the first input, the light emissions originating from switching operations of devices in the first circuit; storing the image as x,y,t data, where x and y indicate a location in the circuit, and t indicates a time increment during the processing of the test input; in a second test operation, applying a second input identical to the first input to an improperly operating, but otherwise equivalent at the schematic level, integrated circuit, under the same conditions; obtaining a second image of light emissions from the second circuit while the second circuit is processing the second input; appropriately transforming the first and second three dimensional images so that they can be compared, and comparing the first and second images to determine the source of the faulty operation of the second circuit.
REFERENCES:
patent: 4755874 (1988-07-01), Esrig et al.
patent: 5032727 (1991-07-01), Cox, Jr. et al.
patent: 5592100 (1997-01-01), Shida et al.
patent: 5598100 (1997-01-01), Maeda et al.
Evans Richard James
Heidel David Frank
Kash Jeffrey Alan
Knebel Daniel Ray
Tsang James Chen-Hsiang
Ballato Josie
Ellenbogen, Esq. Wayne L.
International Business Machines - Corporation
Kobert Russell M.
Scully Scott Murphy & Presser
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