Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Testing or evaluating
Reexamination Certificate
2010-10-19
2011-10-11
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Testing or evaluating
C703S002000
Reexamination Certificate
active
08037447
ABSTRACT:
A method for identifying specification window violations for a system is described. The method includes generating a sample set of input parameters. The system is simulated using the sample set to generate an output set. A mathematical model is best-fit to the output set. A set of desirability functions is defined to an out-of-spec condition. The model is then searched using the desirability functions to identify a worst-case data point. The worst-case data point can then be determined as either being within specification or out of specification.
REFERENCES:
patent: 6356861 (2002-03-01), Singhal et al.
patent: 2004/0034838 (2004-02-01), Liau
Chiang Jack
Martine & Penilla & Gencarella LLP
Oracle America Inc.
Sandoval Patrick
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