IC with cache bit memory in series with scan segment

Details IC with cache bit memory in series with scan segment IC with cache bit memory in series with scan segment

2005-05-24

2005-05-24

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S726000

Reexamination Certificate

active

06898749

ABSTRACT:
Low power delay test capabilities in Scan and Scan-BIST architectures occur by inserting a first cache bit memory between the scan input lead and the serial input to a first scan path segment. When the first segment is serially loaded, the last test bit remains in the first cache bit memory. When a last scan path segment is serially loaded and when the last bit is loaded into the last scan path segment, the last bit in the first cache bit memory is simultaneously loaded into the first scan path segment. This presents the desired stimulus signals to the logic circuits. The next clock signal to the scan path segments then captures the response from the logic circuits.

REFERENCES:
patent: 5768289 (1998-06-01), James

Affiliated with

Also associated with

Rating

IC with cache bit memory in series with scan segment does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with IC with cache bit memory in series with scan segment, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and IC with cache bit memory in series with scan segment will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3448370