Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-05-10
2011-05-10
Tabone, Jr., John J (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S729000, C714S724000, C714S742000
Reexamination Certificate
active
07941717
ABSTRACT:
A method and apparatus for testing an integrated circuit core or circuitry external to an integrated circuit core using a testing circuit passes a test vector from a parallel input of the testing circuit along a shift register circuit. The shift register circuit is configured to bypass one or more cores not being tested and to provide the test vector to a core scan chain of the core being tested. The bypassed cores are configured such that the associated shift register circuit portion is driven to a hold mode in which storage elements of the shift register circuit portion have their outputs coupled to their inputs. This method provides holding of the shift register stages when a core is bypassed and in a test mode, and this means the shift register stages are less prone to errors resulting from changes in clock signals applied to the shift register stages.
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NXP B.V.
Tabone, Jr. John J
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