IC testing apparatus and method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

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Details

714738, G01R 3128, G06F 1100

Patent

active

061382574

ABSTRACT:
Main tester unit tests an IC device for presence of a defect for each of a plurality of addresses of the IC device under predetermined test conditions and stores test results for the individual addresses into a first memory. Curing analysis processing section cures each of the addresses of the IC device determined as defective, on the basis of the test results for the individual addresses stored in the first memory. To this end, the curing analysis processing section may rearrange an address logic of the IC device to replace a physical space of the defective addresses with an extra or redundant address space and thereby place each of the defective addresses in a usable condition. In parallel with the operations by the curing analysis processing section, a defect analysis section acquires, from the main tester unit, the test results for the individual addresses along with data indicative of the predetermined test conditions for storage into a second memory, and analyzes a specific cause of the defect in the IC device on the basis of the stored data in the second memory. With this arrangement, it is possible to acquire information necessary for analyzing the defect in the IC during a curability determining analysis test on a mass production line and thereby can effectively analyze the specific cause of the detected defect.

REFERENCES:
patent: 5381417 (1995-01-01), Loopik et al.
patent: 5790565 (1998-08-01), Sakaguchi

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