IC tap/scan test port access with tap lock circuitry

Details IC tap/scan test port access with tap lock circuitry IC tap/scan test port access with tap lock circuitry

2006-02-21

2006-02-21

Chung, Phung My (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S724000

Reexamination Certificate

active

07003707

ABSTRACT:
Connection circuitry provides for TAP and internal scan test ports to be merged so they both can co-exist and operate from the same set of IC pins and/or core leads or terminals. This arrangement provides for the merged TAP and scan test port interfaces to be selected individually or in groups. Internal Tap Lock circuitry uses only the existing 1149.1 interface signals to produce a Lock Out signal to enable and disable a TMS/CS signal to the TAP circuitry.

REFERENCES:
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patent: 6658632 (2003-12-01), Parulkar et al.
patent: 6671840 (2003-12-01), Nagoya
patent: 2005/0050414 (2005-03-01), Whetsel

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