IC interconnect structures and methods for making same

Details IC interconnect structures and methods for making same IC interconnect structures and methods for making same

1998-09-30

2001-06-12

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S600000, 43

Reexamination Certificate

active

06245663

ABSTRACT:

TECHNICAL FIELD
The present invention relates, generally, to multilevel interconnects used in integrated circuits and, more particularly, to an improved damascene process and structure which utilizes an etch-stop layer deposited after a metal polishing step along with a patterned cap barrier layer.
BACKGROUND ART AND TECHNICAL PROBLEMS
Advanced semiconductor processing technology has permitted the fabrication of integrated circuit devices with sub-micron and sub-half-micron features sizes. This trend toward deep submicron technology (i.e., involving feature sizes less than 0.35 microns) has, in turn, driven the need for multilayer interconnects. As a result, circuit performance in the deep submicron regime is increasingly a function of the delay time of electronic signals traveling between the millions of gates and transistors present on the typical integrated circuit chip. Parasitic capacitance and resistance effects resulting from these otherwise passive interconnect structures must therefore be well-controlled. Toward this end, recent trends emphasize the use of low resistance metals (e.g., copper) in conjunction with low permittivity or low dielectric constant (low-k) dielectrics between the metal lines.
Optical lithography techniques have, for the most part, managed to keep pace with deep sub-micron requirements through the use of off-axis illumination, phase shifting masks, and other methods known in the art. However, the decreasing depth of focus that accompanies this increase in resolution requires the production of highly planar surfaces during intermediary process steps. In light of the need for highly planar surfaces, traditional metal deposition and photolithographic techniques become progressively more ineffective as line widths are scaled down and multiple layers of metal are used. For example, traditional metal deposition techniques can result in poor metal step coverage along the edges of the contact openings. Furthermore, wet chemical etch processes typically used with metals are difficult to control. While dry plasma etching may be employed with many metals, other metals with highly desirable properties (e.g., copper and gold) are generally not amenable to dry etching.
Modern semiconductor processing techniques increasingly employ Chemical-Mechanical Polishing (CMP) to create the interconnect layers, particularly where the number of layers rises above three and the conductive lines themselves are characterized by a high aspect ratio (e.g., lines on the order of 0.25 &mgr;m in width and on the order of 1.0 &mgr;m in height). In a paradigmatic CMP process, a resinous polishing pad (e.g., a polyurethane pad) is employed in conjunction with a mechanically and chemically active slurry. When pressure is applied between the polishing pad and the wafer being polished, mechanical stresses are concentrated on the exposed edges of the adjoining cells in the cellular pad. Abrasive particles within the slurry concentrated on these edges tend to create zones of localized stress at the workpiece in the vicinity of the exposed edges of the polishing pad. This localized pressure creates mechanical strain on the chemical bonds comprising the surface being polished, rendering the chemical bonds more susceptible to chemical attack by the slurry. Thus, with the correct choice of slurry, pressure, and other process conditions, a highly planar surface may be formed on the wafer. For additional information regarding CMP process, see, for example, Karlsrud, U.S. Pat. No. 5,498,196, issued March, 1996; Arai, el al., U.S. Pat. No. 5,099,614, issued March, 1992; and Arai, et al., U.S. Pat. No. 4,805,348, issued February, 1989. The entire contents of these references are hereby incorporated by reference.
A fabrication method which employs CMP techniques and which addresses many of the above concerns is the so-called “damascene” process. Damascening acquired its name from an ornamental technique, generally attributed to metal-workers in ancient Damascus, which involved scribing or incising patterns into steel (most often swords) then filling the resulting grooves with gold or silver prior to final polish. Similarly, the modern semiconductor analog of this process involves, in the broadest sense, forming patterns in a dielectric layer, filling the resulting pattern with interconnect metal, then polishing away the excess metal on the wafer surface and leaving inlaid interconnect metal features.
There are two major classes of damascene processes: single-damascene and dual-damascene. These two processes are illustrated in highly simplified form in
FIGS. 1A and 1B
(details of the various intermediary steps are discussed in further detail below). Briefly, and with reference to
FIG. 1A
, a single damascene process involves making contact to a lower conductor
102
(formed, for example, on substrate
107
) by patterning dielectric
106
and forming a conductive plug
104
in dielectric layer
106
, then patterning dielectric layer
110
and forming the actual interconnect metallization
108
in patterned dielectric layer
110
. In a dual-damascene process (FIG.
1
B), the interconnect layer
108
and plug
104
are formed in a single dielectric layer
106
by patterning both the via and the trench pattern into dielectric
106
, then filling them simultaneously with metal. While more steps are required in a single-damascene process, this method does not suffer from many of the difficulties inherent in the dual-damascene process. For example, it is difficult to etch both a hole for plug
104
and a trench for wiring
108
within a single layer having a very high aspect ratio. Similarly, it is difficult to fill the high aspect ratio dual damascene structures to form plug
104
and wiring
108
with metals.
In cases where controlling interconnect wiring trench-depth is critical, a single-damascene process utilizing an “etch-stop” layer is often employed. In this regard, an illustrative singledamascene process is disclosed in U.S. Pat. No. 5,612,254, issued Mar. 18, 1997 to Mu et al., entitled
Methods of Forming an Interconnect on a Semiconductor Substrate
(hereinafter “Mu”).
Referring now to
FIGS. 2A-2F
, which are taken from the Mu drawings, a silicon nitride layer
23
(the etch stop layer) and borophosphosilicate glass (BPSG) layer
22
are deposited over a substrate
20
which includes a diffused region
21
(FIG.
2
A). These two layers are then patterned to form a contact opening
30
(
FIG. 2B
) which is then filled, using conventional techniques, with a contact plug
41
(FIG.
2
C). Mu discloses a method of forming plug
41
which involves anisotropic etching of CVD-deposited tungsten and titanium nitride layers. Other known methods of forming plug
41
include, for example, using a CMP process to polish away the excess metal on the wafer surface after plug metal deposition.
After forming plug
41
, a layer
50
of silicon dioxide is deposited and dry-etched to create interconnect wiring trenches
51
(FIG.
2
D). In this regard, a key aspect of the Mu disclosure lies in the etch-stop function of layer
23
. That is, to the extent that layers
50
and
23
exhibit different etch rates during a particularly chosen etch process (for example Reactive Ion Etching (RIE)), etching of layer
50
proceeds until layer
23
is reached, thus producing trench
51
having a relatively uniform depth. In subsequent steps, barrier metal
60
and metal layer
61
are deposited (FIG.
2
E), and the top surface is planarized using CMP to remove the excess top metal and to form interconnect wiring within trenches
61
.
This and other known methods are unsatisfactory in many respects. Prior art processes, for example, utilize an etch stop layer which is deposited before CMP of the previous metal plug layer (e.g., layer
23
in
FIG. 2C
is deposited prior to formation of contact plug
41
). As a result, significant loss of etch stop material is common during the metal CMP process. This dielectric loss during CMP is due to a number of factors. First, there is significant dielectric erosion of the etch stop

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