Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2008-07-29
2010-12-28
Soward, Ida M (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S621000, C257S622000, C257S700000, C257SE21578, C257SE21585, C257SE21586, C257SE21587, C257SE21588, C257SE21597
Reexamination Certificate
active
07859114
ABSTRACT:
An IC chip and design structure having a TWV contact contacting the TWV and extending through a second dielectric layer over the TWV. An IC chip may include a substrate; a through wafer via (TWV) extending through at least one first dielectric layer and into the substrate; a TWV contact contacting the TWV and extending through a second dielectric layer over the TWV; and a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting the TWV contact.
REFERENCES:
patent: 5970367 (1999-10-01), Wanlass
patent: 6069068 (2000-05-01), Rathore et al.
patent: 6130161 (2000-10-01), Ashley et al.
patent: 6133139 (2000-10-01), Dalal et al.
patent: 6162743 (2000-12-01), Chu et al.
patent: 6258710 (2001-07-01), Rathore et al.
patent: 6287954 (2001-09-01), Ashley et al.
patent: 6294835 (2001-09-01), Dalal et al.
patent: 6348731 (2002-02-01), Ashley et al.
patent: 6355528 (2002-03-01), Ishida et al.
patent: 6429099 (2002-08-01), Christensen et al.
patent: 6657242 (2003-12-01), Norstrom et al.
patent: 6964897 (2005-11-01), Bard et al.
patent: 7247560 (2007-07-01), Kinner et al.
patent: 7253527 (2007-08-01), Tanida et al.
patent: 2004/0262767 (2004-12-01), Matsuo
patent: 2007/0190692 (2007-08-01), Erturk et al.
patent: 2009/0039471 (2009-02-01), Katagiri
patent: 2009/0068835 (2009-03-01), La Tulipe et al.
patent: 2009/0160058 (2009-06-01), Kuo et al.
patent: 2009/0191708 (2009-07-01), Kropewnicki et al.
patent: 2009/0269905 (2009-10-01), Chen et al.
patent: 2009/0302480 (2009-12-01), Birner et al.
patent: 2009/0315154 (2009-12-01), Kirby et al.
U.S. Appl. No. 12/181,359, Amendment To Office Action dated May 5, 2010, filed Jul. 12, 2010, 11 pages.
U.S. Appl. No. 12/181,359, Office Action dated May 5, 2010, 9 pages.
Lindgren Peter J.
Sprogis Edmund J.
Stamper Anthony K.
Canale Anthony J.
Hoffman Warnick LLC
International Business Machines - Corporation
Soward Ida M
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