I/O planning with lock and insertion features

Details I/O planning with lock and insertion features I/O planning with lock and insertion features

2005-04-27

2009-06-02

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

07543261

ABSTRACT:
A method of operation for an input/output assignment tool is disclosed. The method generally includes the steps of (A) generating a graphic presentation to a user displaying (i) a circuit icon having a plurality of pin icons and (ii) a plurality of signal icons, (B) moving a first of the signal icons within the graphic presentation to a first of the pin icons in response to a move command from the user and (C) indicating an acceptance of an association between the first signal icon and the first pin icon in response to the association passing a rule.

REFERENCES:
patent: 6063132 (2000-05-01), DeCamp et al.
patent: 7076751 (2006-07-01), Nixon et al.
patent: 7100139 (2006-08-01), Anderson et al.
patent: 2005/0188336 (2005-08-01), Mortensen et al.
patent: 2006/0075372 (2006-04-01), Gryba

Affiliated with

Also associated with

Rating

I/O planning with lock and insertion features does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with I/O planning with lock and insertion features, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and I/O planning with lock and insertion features will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4069275