Method for enhancing electrode surface area in DRAM cell...

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S306000, C257SE21012

Reexamination Certificate

active

07573121

ABSTRACT:
Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is fabricated by forming a texturizing underlayer and then depositing a conductive material thereover. In one embodiment of a method of forming the lower electrode, the texturizing layer is formed by depositing a polymeric material comprising a hydrocarbon block and a silicon-containing block, over the insulative layer of a container, and then subsequently converting the polymeric film to relief or porous nanostructures by exposure to UV radiation and ozone, resulting in a textured porous or relief silicon oxycarbide film. A conductive material is then deposited over the texturizing layer resulting in a lower electrode have an upper roughened surface. In another embodiment of a method of forming the lower electrode, the texturizing underlayer is formed by depositing overlying first and second conductive metal layers and annealing the metal layers to form surface dislocations, preferably structured as a periodic network. A conductive metal is then deposited in gaseous phase, and agglomerates onto the surface dislocations of the texturizing layer, forming nanostructures in the form of island clusters. The capacitor is completed by depositing a dielectric layer over the formed lower electrode, and forming an upper capacitor electrode over the dielectric layer. The capacitors are particularly useful in fabricating DRAM cells.

REFERENCES:
patent: 3366515 (1968-01-01), Fraser et al.
patent: 5102832 (1992-04-01), Tuttle
patent: 5407534 (1995-04-01), Thakur
patent: 5418180 (1995-05-01), Brown
patent: 5612560 (1997-03-01), Chivukula et al.
patent: 5616959 (1997-04-01), Jeng
patent: 5753948 (1998-05-01), Nguyen et al.
patent: 5789268 (1998-08-01), Chivukula et al.
patent: 5815304 (1998-09-01), Choi
patent: 5851898 (1998-12-01), Hsia et al.
patent: 5937294 (1999-08-01), Sandhu et al.
patent: 5990559 (1999-11-01), Marsh
patent: H1824 (1999-12-01), Johnsen et al.
patent: 6022595 (2000-02-01), McDonald et al.
patent: 6033967 (2000-03-01), Li et al.
patent: 6051869 (2000-04-01), Pan et al.
patent: 6143646 (2000-11-01), Wetzel
patent: 6153899 (2000-11-01), Ping
patent: 6180485 (2001-01-01), Parekh et al.
patent: 6188097 (2001-02-01), Derderian et al.
patent: 6190992 (2001-02-01), Sandhu et al.
patent: 6194264 (2001-02-01), Ping et al.
patent: 6197634 (2001-03-01), Schuegraf
patent: 6281543 (2001-08-01), Al-Shareef et al.
patent: 6284589 (2001-09-01), Lim et al.
patent: 6537925 (2003-03-01), Kim et al.
patent: 6613586 (2003-09-01), Bailey
patent: 2001/0001210 (2001-05-01), Rhodes et al.
patent: 2001/0023110 (2001-09-01), Fukuzumi et al.
patent: 2002/0005536 (2002-01-01), Schindler et al.
patent: 2002/0084471 (2002-07-01), Won et al.
patent: 2005/0101099 (2005-05-01), Kim et al.
patent: 2005/0194628 (2005-09-01), Kellar et al.
patent: 2006/0263977 (2006-11-01), Kim et al.
patent: 0567748 (1993-03-01), None
patent: 04-216662 (1992-08-01), None
patent: 5-075056 (1993-03-01), None
patent: 06-020958 (1994-01-01), None
patent: 10-107026 (1998-04-01), None
patent: 11-220101 (1999-08-01), None
patent: 2000-191324 (2000-07-01), None
patent: 01/95377 (2001-12-01), None
patent: 01/95378 (2001-12-01), None
Chan, Vanessa et al., Ordered Bicontinuous Nanoporous and Nanorelief Ceramic Films from Self Assembling Polymer Precursors, Science, Nov. 26, 1999, vol. 286, pp. 1716-1719.
Lewis, P.A. et al., Silicon Nanopillars Formed with Gold Colloidal Particle Masking, J. Vac. Sci. Technol., B 16(6), Nov./Dec. 1998, pp. 2938-2941.
Phely-Bobin et al., Preferential Self-Assembly of Surface-Modified Si/Siox Nanoparticles on UV/Ozone Micropatterned Poly(dimethylsiloxane) Films, Adv. Mater., 2000, 12, No. 17, Sep. 1, pp. 1257-1261.
Yang, G.R. et al., Increase of Deposition Rate of Vapor Deposited Polymer by Electric Field, DUMIC Conference, 1996 ISMIC, Feb. 20-21, 1996, pp. 214-219.
Bromann, K. et al., Self-Organized Growth of Cluster Arrays, Eur. Phys. J.D., 9, 1999, pp. 25-28.
Guarini et al., Nanoscale patterning using self-assembled polymers for semiconductor applications, J. Vac. Sci Technol. B. 19(6) (Nov./Dec. 2001) 2784-2788.
Brune et al., Self-organized growth of nanostructure arrays on strain-relief patterns, Nature, 394 (Jul. 1998) 451-453.
C.L. Mirley, et al., A Room Temperature Method for the Preparation of Ultrathin SiOx Films from Langmuir-Blodgett Layers, Langmuir, vol. 11, No. 4, Apr. 1995, American Chemical Society, pp. 1049-1052.
R. Schuster, et al., Stress Relief via Island Formation of an Isotropically Strained Bimetallic Surface Layer: The Mesoscopic Morphology of the Ag/Pt (111) Surface Alloy, The Physical Society, Nov. 15, 1996, vol. 54, No. 19, pp. 13476-13479.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method for enhancing electrode surface area in DRAM cell... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for enhancing electrode surface area in DRAM cell..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for enhancing electrode surface area in DRAM cell... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4069274

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.