Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-03-30
2002-05-07
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185110, C365S185190
Reexamination Certificate
active
06385093
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to Electrically Erasable Programmable Read Only Memory (EEPROM), and more particularly relates to a system and method for reducing band-to-band tunneling current during a Flash EEPROM erase cycle via memory I/O partitioning of the erase cycle.
BACKGROUND OF THE INVENTION
Memory devices, such as Electrically Erasable Programmable Read Only Memories (EEPROMs), are an important architectural component in modern computing systems. These systems affect many aspects of society ranging from the home to business and education. For example, wireless systems, such as cell phones, have become a staple in many people's day-to-day lives. As this technology and others have advanced however, system requirements have become increasingly demanding for systems designers and architects. One important demand has been the need for smaller memory packaging with increased memory density in order to provide ever more functionality in smaller portable computing systems such as cell phones and other hand held systems such as Personal Digital Assistants (PDAs) and pagers.
Flash EEPROMs enable computing systems to store large amounts of program data that generally provide instructions to an associated computer processing system. An advantage to Flash memory is the ability to electrically re-program the memory via program and erase operations associated with the Flash. Thus, if a manufacturer desires to correct a product bug and/or provide an updated product feature, the Flash memory may be easily re-programmed without having to replace components within the given product. As described above, as technology demands have increased, density and packaging requirements for Flash memories have also steadily increased. Unfortunately, as memory density requirements increase, challenges relating to Flash program and erase operations have increased.
One such challenge associated with Flash memories relates to increased current requirements during memory cell/sector erase operations. Memory cells generally may be described by a MOS structure wherein a voltage is applied to a cell gate element with respect to cell drain and source elements in order to store or remove charge associated with charge trapping regions within the cell structure. Erase operations to a cell may be provided, for example, by applying a negative voltage to the gate element and an elevated voltage to the drain element via a drain pump. As an erase is performed, a current known as band-to-band tunneling current is generated by the drain pump as a result of removing stored electrons from the charge trapping regions of the cell structure. As is the case with high-density flash structures, hundreds of thousands or millions of such cells may be programmed/erased concurrently. Consequently, band-to-band tunneling current requirements for the drain pump power supply may increase dramatically depending on the particular type of flash technology employed and the amount of cells that are concurrently erased/programmed.
Increased band-to-band tunneling current requirements, however, may cause problems for the associated drain pump. For example, increased current may cause increased IR drops within the memory device and therefore lead to a reduction in drain pump output voltage. If the drain pump output voltage is reduced, errors may occur during Flash erase or programming operations, wherein memory cells are improperly or impartially erased/programmed. Presently, conventional Flash erase systems may cause increased band-to-band tunneling current problems. This may occur since entire memory segments (e.g., 1 Megabyte, ½ Megabyte) are generally programmed with a single erase pulse and/or sequence. Consequently, it would therefore be desirable to improve upon conventional Flash erase systems and methods in order to reduce band-to-band current requirements.
SUMMARY OF THE INVENTION
The present invention relates to a system and method for reducing band-to-band tunneling current requirements during Flash EEPROM erase operations. This may be achieved by partitioning a sector of a Flash memory into N I/O subsectors, wherein N is an integer, and providing an erase pulse to each of the N I/O subsectors, respectively. Band-to-band tunneling current requirements are reduced since each I/O subsector erase operation requires less tunneling current than required for an entire sector erase operation. Furthermore, drain pumps supplying the band-to-band tunneling current may be designed with lower power and size requirements than conventional systems.
As will be described in more detail below, I/O and related erase partitioning may be applied during some erase operations and not applied during subsequent erase operations. For example, a sector may be erased via a plurality of pulses applied to individual I/O subsectors of the sector. After the partitioned erase, a verify operation commences wherein the sector is checked to determine if all the memory locations have been properly erased. If all the memory locations have not been erased, a subsequent partitioned erase sequence may commence with an associated subsequent verify sequence. If all the memory locations have still not been erased properly after the subsequent verify sequence, a full sector erase may then be initiated wherein all the N I/O subsectors are erased concurrently. Subsequent full sector erases may be commenced since most of the cells in the partitioned sector have been previously erased during the partitioned erase sequence described above. Thus, full sector erases after initial erase partitioning may be commenced without overloading the associated drain pump.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.
REFERENCES:
patent: 5339279 (1994-08-01), Toms et al.
patent: 5699298 (1997-12-01), Shiau
patent: 5814853 (1998-09-01), Chen
patent: 6049479 (2000-04-01), Thurgate et al.
patent: 6057575 (2000-05-01), Jenq
patent: 6188609 (2001-02-01), Sunkavalli
Bautista, Jr. Edward V.
Hamilton Darlene
Kurihara Kazuhiro
Lee Weng Fook
Pan Feng
Advanced Micro Devices , Inc.
Eschweiler & Associates LLC
Zarabian A.
LandOfFree
I/O partitioning system and methodology to reduce... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with I/O partitioning system and methodology to reduce..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and I/O partitioning system and methodology to reduce... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2867771