Hydrogenated silicon carbide as a liner for self-aligning...

Details Hydrogenated silicon carbide as a liner for self-aligning... Hydrogenated silicon carbide as a liner for self-aligning...

2000-08-16

2002-03-26

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S765000

Reexamination Certificate

active

06362094

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to semiconductor integrated circuit manufacturing and, more specifically, to a method of forming a liner of hydrogenated silicon carbide within a via prior to forming a self-aligned contact.
BACKGROUND OF THE INVENTION
In the highly competitive electronics marketplace of today, the functionality of most similar devices has become fairly similar. Therefore, more emphasis is being placed on the speed of a device as the standard by which competing electronics are measured. In general, to both private consumers and businesses alike, an electronic device is more desirable if the electronics, e.g., the processor(s), are faster than the competing electronics.
Many approaches to increasing the speed of an integrated circuit have been tried. Among successful areas of research has been the relatively recent disclosure of the ability to use copper as a conductor in place of aluminum. Until fairly recently, most integrated circuits were constrained to the use of aluminum and tungsten as contacts or interconnects. However, due to the advancements in processing, copper is quickly becoming a highly desirable metal to use in integrated electronics. Additionally, copper, which is significantly faster as a conductor than aluminum, is also relatively inexpensive. Therefore, the search for other approaches to increase speed is now consistently focused on decreasing inter-device distances to increase the integrated circuit operating speed in general. One such approach is to drive the integrated circuits to a higher device density in an effort to increase the operating speed. Today, with feature sizes approaching 0.12 &mgr;m, every factor is being examined to increase operating speed.
Forming self-aligned contacts (SACs) between the active devices and the interconnect levels is one of the approaches being used to achieve higher device densities. SACs are formed by exploiting the etch selectivity between either undoped, boron-doped, phosphorus-doped, or boron and phosphorous-doped oxides and silicon nitride (SiN). That is, a via is formed in the layers using selective etches over the intended contact point and then filled with conductive metal.
However, SAC processes using the conventional materials listed above are becoming much less useful as the device sizes approach 0.12 &mgr;m. At these device sizes, high density plasma dielectrics are required to fill more aggressive aspect ratio gaps, that, in turn, have less selectivity to the silicon nitride liner material. Furthermore, the relatively high dielectric constant of the silicon nitride liner poses a concern over increased parasitic capacitance. Also, the relatively high dielectric constant of the SiN liner poses concern for increased parasitic capacitance in the resultant device. Some attempts have been made to improve etch selectivity by increasing the dopant levels or using lower density fill materials, such as ozone reacted oxides. However, the higher dopant concentration and porous fill materials are inherently unstable.
Accordingly, what is needed in the art is an improved method for forming self-aligned contacts in vias of integrated circuits that do not suffer from the deficiencies of the prior art.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides, in one embodiment, a method of fabricating a self-aligning contact opening comprising: (a) forming a dielectric layer over a semiconductor substrate and gate electrodes located on the semiconductor substrate, (b) forming a carbide liner over the dielectric layer, and (c) etching at least a portion the carbide liner to form a self-aligning contact opening between the gate electrodes.
In an alternative embodiment, forming a carbide liner includes forming a hydrogenated silicon carbide liner. The step of forming a carbide liner may include forming a carbide liner with a chemistry including methyl silane, dimethyl silane, trimethyl silane, or tetramethyl silane. Alternatively, the carbide liner may be formed with a chemistry including oxygen in the form of nitrous oxide, carbon dioxide, or oxygen. An alternative chemistry may include methane, butane and acetylene.
Different embodiments may include Various processing parameters, such as temperature, pressure and radio frequency (rf) power. For example in one embodiment the carbide liner may be formed at a temperature ranging from about 250° C. to about 400° C. In a related embodiment, forming a carbide liner includes forming a carbide liner at a pressure ranging from about 2.5 Torr to about 10.0 Torr. In another embodiment, the method may include forming a carbide liner at an rf power ranging from about 200 W to about 600 W at about 13.56 MHz.
In yet another embodiment, the method may further comprise forming an oxide layer over the carbide liner and etching at least a portion of each of the oxide layer and the carbide liner. In a related embodiment, the method includes etching with an etch comprising an appropriate mixture of fluorocarbons, hydrofluorocarbons, oxygen, and diluent (e.g., Ar, N2, etc.). Moreover, the mixture may contain any combination of these gases.
The method may include etching with a first chemistry that is selective to the carbide liner as compared with the dielectric layer. In a further aspect of this embodiment, the method may further include etching with a second chemistry that is selective to the carbide liner as compared with the oxide liner. In a particular aspect of this embodiment, etching with a second chemistry includes etching with an etch comprising an appropriate mixture of fluorocarbons, hydrofluorocarbons, oxygen, and diluent (e.g., Ar, N2, etc.). In an advantageous embodiment, the amount of oxygen and/or nitrogen may be higher than the first chemistry disclosed above. In yet another embodiment, the method further comprises removing a portion of the dielectric layer.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.


REFERENCES:
patent: 5859458 (1999-01-01), Hsueh et al.
patent: 6054379 (2000-04-01), Yau et al.
patent: 6066555 (2000-05-01), Nulty et al.

Affiliated with

Also associated with

Rating

Hydrogenated silicon carbide as a liner for self-aligning... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Hydrogenated silicon carbide as a liner for self-aligning..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hydrogenated silicon carbide as a liner for self-aligning... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2839328