Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-11-24
2004-11-30
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S424000
Reexamination Certificate
active
06825087
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates in general to semiconductor technology, and in particular to forming an enhanced trench for applications such as trench MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).
Power field effect transistors, such as MOSFETs are well known in the semiconductor industry. One type of MOSFET is a trench MOSFET. Trench MOSFETs typically include a substrate upon which an epitaxial layer is grown; doped source regions of a first charge type (i.e. p or n); a doped well of an opposite charge type from the source regions; one or more trenches that extend into the body of the well(s); a dielectric layer covering the inner wall(s) of the trench(es); a conductive material (e.g. polysilicon) covering the inner wall(s) of the dielectric layer(s), which embody the gate(s) of the trench MOSFET(s); and one or more optional doped heavy body (bodies) of the same charge type as the well(s).
It is desirable that a trench, formed in the fabrication of a trench MOSFET, extend substantially vertically into the body of the well(s). This allows a higher density of trenches to be formed across the semiconductor substrate. Because an anisotropic etch etches substantially in one direction, it is preferred compared to other isotropic etches.
One undesirable side effect that results from use of an anisotropic etch, however, is the sharp edges that form along the top and bottom corners of the trench. If the trench has sharp edges at its corners, it becomes difficult to grow a gate oxide that is uniform in thickness. A gate oxide that varies in thickness becomes subject to nonuniform electric fields along the trench MOSFET channel region, which degrades the performance of the trench MOSFET. This is exacerbated by the fact that a trench MOSFET is typically made up of a large number of trenches, either in a stripped or cellular pattern. In a trench MOSFET, wherein all trenches are fabricated without rounded corners, the peak electric fields tend to move towards the trench corners. By contrast, a series of trenches having rounded corners causes the peak electric fields to move away from the trench corners and toward central locations between adjacent trenches.
One method of smoothing out the corners of a trench is to administer a rounding etch to the trench followed by a downstream plasma etch. However this method, can cause added damage to the silicon and introduces several additional processing steps in the overall process of manufacturing the rounded trench.
It would be desirable, therefore, if a solution were available that could round the trench corners without having to add additional processing steps in the overall process of forming the enhanced trench.
Another critical step in the manufacture of a trench MOSFET is the forming of an oxide layer for the gate electrode, which is as defect-free as possible. This requires that the underlying silicon, upon which the oxide layer is to be grown, itself be as crystalline and as defect-free as possible, so that traps or other defects do not readily form at the silicon/dielectric interface and/or propagate into the dielectric material as it is grown. Such defects can increase the charge density in the oxide layer, thereby lowering the gate oxide breakdown voltage (often characterized by charge breakdown, QBD). A low QBD signifies a trench MOSFET with degraded performance capabilities.
To achieve a high-quality gate oxide with a high QBD, the native oxide that forms on the walls of the silicon trench is typically removed, after which a high-quality gate oxide is grown using thermal oxidation. (A “native oxide” is an oxide that naturally grows on a bare silicon surface when it is exposed to air. ) While a native oxide is for the most part crystalline, it is also prone to defect capture and retention.
One method of removing the native oxide is to perform a wet etch using hydrofluoric (HF) acid. However, use of HF is undesirable in that it not only leaves behind impurity byproducts associated with fluorine, it also calls for additional processing steps (e.g. cleaning steps including washing and drying).
Another prior art method of preparing the trench for gate oxidation is to grow a sacrificial oxide, whereby an oxide is grown and then stripped to remove defects. Unfortunately, just as with the HF etch, such a method requires additional processing steps.
It would be desirable, therefore, if a solution were available that could both prepare the walls of the silicon trench for growing a high-quality gate oxide and, at the same time, round the corners of the trench without having to add additional processing steps in the overall process of manufacturing the trench.
The present invention addresses these problems, by rendering unnecessary the previously required prior art rounding and plasma etch steps (used to round the trench corners) and HF or sacrificial oxide and strip steps (to effect defect reduction prior to growing the gate oxide).
SUMMARY OF THE INVENTION
The present invention provides a method of forming a trench in an epitaxial layer grown on a semiconductor substrate, the trench having rounded corners at the top and bottom ends of the trench. The rounded corners are formed, following formation of the trench by an anneal process, which is preferably performed at a combined high temperature and low pressure so as to prevent the epitaxial layer from melting but is sufficient enough to cause the atoms of the epitaxial layer to migrate and form low stress relief points at the trench corners. The strains at the corners of the trench corners are believed to be stress relief points, which cause the trench corners to conform to an elliptical (or “round”) shape.
In a first aspect of the invention, a trench is initially formed that extends a predetermined distance into a semiconductor substrate. Preferably, this trench formation step is performed using an anisotropic etch. Following the trench formation step, the trench is annealed, preferably with hydrogen gas. The anneal step has the benefit of not only reducing the defect density on the walls of the trench but also providing the desirable effect of rounding the top and bottom corners of the trench.
In a second aspect of the invention the rounded trench is formed into an epitaxial layer, previously grown on a semiconductor substrate. The process of annealing the trench is substantially similar to the annealing step described in the first aspect of the invention.
In a third aspect of the invention a method of forming a trench with rounded corners is disclosed, which includes the steps of: (a) providing a semiconductor substrate; (b) forming a masking layer on the major surface of the substrate; (c) selectively etching, through the masking layer to the major surface of the substrate, to define a trench opening access; (d) anisotropically etching, from the trench opening access and into the body of the substrate to form a trench; (e) removing the selectively etched masking layer; and (f) annealing the trench so that corners at the open and closed ends of the trench become rounded.
In a fourth aspect of the invention, a method of forming a trench MOSFET having trench(es) with rounded corners is disclosed, the rounded corners formed using the anneal step in accordance with the present invention.
In a fifth aspect of the invention, a trench MOSFET is disclosed, the trench(es) of the trench MOSFET having rounded corners formed using the anneal step in accordance with the present invention.
Other features and advantages of the invention will be apparent from the following detailed description and the drawings.
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Madson Gordon K.
Sharp Joelle
Fairchild Semiconductor Corporation
Nelms David
Townsend and Townsend / and Crew LLP
Vu David
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