Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-09-21
2003-05-27
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S289000, C438S291000, C438S308000
Reexamination Certificate
active
06569741
ABSTRACT:
BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to integrated circuit structures and fabrication methods, and more particularly to formation of gate structures in an integrated circuit process.
BACKGROUND
Integrated circuits are made up of millions of devices, and the drive for greater computational power and speed drives devices to smaller and smaller scales. This allows devices to be more densely packed, which allows more devices to be placed on a single chip one important constraint on device size is the ability to form high quality low defect very thin gate dielectrics.
Surfaces of solids and interfaces between materials play an important role in semiconductor technology. The ability to lay a thin oxide layer for the gate structure depends in part on the surface of the silicon substrate. It is highly desirable to have a very smooth surface prior to gate oxide formation.
Gate oxide is a very important step in integrated circuit construction, and the need to form a high quality, defect free, very thin oxide without contamination makes gate oxidation a key step in MOS processing. The gate oxide needs to be as thin as possible, in the range of angstroms. The gate oxide will determine many qualities that affect a transistor's function. Though the oxide is usually made very thin, any holes in the oxide can cause problems such as shorting the substrate to the gate. The smoothness of the underlying surface affects the quality of the gate oxide layer greatly because of this.
Typically, to get a high quality oxide, the previous oxide layer is stripped from the gate region and a new gate oxide is formed. The new gate oxides are usually formed slowly and carefully by dry oxidation. The remaining gate material is then normally formed over the gate oxide. Polysilicon is the standard gate material and is usually formed using CVD methods.
One of the most important uses for ion implantation is for MOS gate threshold voltage adjustment. No current can flow between the source and drain until the channel forms beneath the gate, conductively connecting the source and drain. The amount of voltage necessary for this to occur is the threshold voltage of the device. The threshold voltage is very sensitive to the dopant concentration of the channel. Threshold voltage is an important parameter, in part because a lower threshold voltage means fewer power supplies and faster circuits.
The work function between the gate material and the doping level in the semiconductor determines the threshold voltage. Ion implantation is a typical technique used to control doping levels in semiconductors.
Ion implantation is used to inject dopants into a material. Unlike diffusion, which is a chemical process, ion implantation is a physical process. Dopant atoms are ionized and accelerated in a beam which is directed at the required wafer location. The dopant atoms enter the target material and come to rest below the surface. Ion implantation is the preferred doping technique for dense and small feature circuits because of its control and the lack of lateral diffusion.
Ion implantation of dopants into the channel is typically accomplished before the gate layers are formed. The timing of the implant depends on other process steps, since some of the environmental requirements of process steps (such as high temperature) can cause redistribution of implants.
Hydrogen Anneal Before Gate Oxidation
The present application discloses an innovative process for smoothing a surface prior to gate dielectric formation. The process uses a hydrogen anneal, followed by formation of part of the gate structure (preferably the gate dielectric, followed by a layer of TiN, a layer of polysilicon, an oxide layer, and a nitride layer). The channel implant is done after at least some of the gate structure is formed, preferably those listed above. This prevents diffusion of the implanted ions, which could occur if the silicon surface were annealed before the gate structure were formed.
Advantages of the disclosed methods and structures, in various embodiments, can include one or more of the following:
hydrogen anneal leaves Si surface clean and reconstructed;
better gate dielectric integrity, especially for thinner gate dielectrics;
more uniform transistor characteristics.
REFERENCES:
patent: 5362685 (1994-11-01), Gardner et al.
patent: 6008128 (1999-12-01), Habuka et al.
patent: 6207591 (2001-03-01), Aoki et al.
Houston Theodore W.
Unnikrishnan Sreenath
Dang Trung
Garner Jacqueline J.
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