Hybrid transistor based power gating switch circuit and method

Details Hybrid transistor based power gating switch circuit and method Hybrid transistor based power gating switch circuit and method

2011-01-11

2011-01-11

Ghyka, Alexander G (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S276000, C438S301000, C326S033000, C326S121000, C257SE21616

Reexamination Certificate

active

07867858

ABSTRACT:
A method includes forming a first transistor having a first gate dielectric thickness and a first source/drain extension depth, a second transistor having a second gate dielectric thickness and the first source/drain extension depth, and a third transistor having the second gate dielectric thickness and a second source/drain extension depth. The second source/drain extension depth is greater than the first source/drain extension depth. The second gate dielectric thickness is greater than the first gate dielectric thickness. The first transistor is used in a logic circuit. The third transistor is used in an I/O circuit. The second transistor is made without extra processing steps and is better than either the first or third transistor for coupling a power supply terminal to the logic circuit in a power-up mode and decoupling the power supply terminal from the logic circuit in a power-down mode.

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PCT Search Report and Written Opinion, PCT/US2009/033195, mailed Aug. 27, 2009.

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