Hybrid solid-state memory system having volatile and...

Static information storage and retrieval – Read/write circuit

Reexamination Certificate

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C365S185110, C365S185330

Reexamination Certificate

active

07554855

ABSTRACT:
A hybrid solid-state memory system is provided for storing data. The solid-state memory system comprises a volatile solid-state memory, a non-volatile solid-state memory, and a memory controller. Further, a method is provided for storing data in the solid-state memory system. The method comprises the following steps. A write command is received by the memory controller. Write data is stored in the volatile memory in response to the write command. Data is transferred from the volatile memory to the non-volatile memory in response to a data transfer request.

REFERENCES:
patent: 5404460 (1995-04-01), Thomsen et al.
patent: 5430859 (1995-07-01), Norman et al.
patent: 5475854 (1995-12-01), Thomsen et al.
patent: 5600596 (1997-02-01), Shirakihara
patent: 5806070 (1998-09-01), Norman et al.
patent: 6009479 (1999-12-01), Jeffries
patent: 6144576 (2000-11-01), Leddige et al.
patent: 6148363 (2000-11-01), Lofgren et al.
patent: 6304921 (2001-10-01), Rooke
patent: 6317812 (2001-11-01), Lofgren et al.
patent: 6418506 (2002-07-01), Pashley et al.
patent: 6453365 (2002-09-01), Habot
patent: 6567904 (2003-05-01), Khandekar et al.
patent: 6658509 (2003-12-01), Bonella et al.
patent: 6715044 (2004-03-01), Lofgren et al.
patent: 6763424 (2004-07-01), Conley
patent: 6775184 (2004-08-01), Park et al.
patent: 6928501 (2005-08-01), Andreas et al.
patent: 6944697 (2005-09-01), Andreas
patent: 6950325 (2005-09-01), Chen
patent: 6996644 (2006-02-01), Schoch et al.
patent: 7031221 (2006-04-01), Mooney et al.
patent: 7032039 (2006-04-01), DeCaro et al.
patent: 7050322 (2006-05-01), Zambrano
patent: 7073022 (2006-07-01), El-Batal et al.
patent: 2001/0026487 (2001-10-01), Koga
patent: 2002/0120820 (2002-08-01), Higuchi et al.
patent: 2003/0221061 (2003-11-01), El-Batal et al.
patent: 2004/0148482 (2004-07-01), Grundy et al.
patent: 2007/0076479 (2007-04-01), Kim et al.
patent: 2007/0109833 (2007-05-01), Pyeon et al.
patent: 2007/0168698 (2007-07-01), Coulson et al.
patent: 2007/0177430 (2007-08-01), Morio
patent: 2008/0005518 (2008-01-01), Gillingham et al.
patent: 2008/0084727 (2008-04-01), Norman
patent: 2008/0130386 (2008-06-01), Pyeon
patent: 5566306 (1993-10-01), None
patent: 1717985 (2006-11-01), None
June Lee; et al. “A 90-nm CMOS 1.8-V 2-Gb NAND Flash Memory for Mass Storage Applications;” Jun. 23, 2003; pp. 1934 to 1942.
PCT International Search Report and Written Opinion issued by the Canadian Intellectual Property Office dated Apr. 10, 2008 for corresponding International Application No. PCT/CA2007/002304 filed Dec. 18, 2007.
King et al., “Communicating with Daisy Chained MCP42XXX Digital Potentiometers”, 2001 Microtechnology Inc.
Microchip Product Description 24AA1025/24LC1025/24FC1025, 2006 Michropchip Technology Inc.
Intel, “Intel StrataFlash Wireless Memory (L18)”, Order No. 251902, Revision 010, Aug. 2005.
Intel, “How to Use OTP Registers for Security Applications”, Application Note 717, Oct. 1999, Order No. 292265-001.
Samsung Electronics Product Description “K9XXG08Uxm”.
Atmel Product Description “8-megabit 2.5-volt Only or 2.7-volt Only DataFlash”, AT45DB081B.
The 12C-Bus Specification, Version 2.1, Jan. 2000.
Spansion Data Sheet, S70GL01GN00 MirrorBit Flash 1024 Megabit, 3.0 Volt-only Page Mode Flash Memory Featuring 110 mm MirrorBit Process Technology, Jun. 1, 2005.
Silicon Storage Technology, Inc. Specification, “16 Mbit SPI Serial Flash”.
ST Product Description, “2 Mbit, Low Voltage, Serial Flash Memory With 40 MHz SPI bus Interface”, Aug. 2005.
Hyper Transport Technology Consortium, HyperTransport I/O Link Specification, Revision 3.00, Apr. 21, 2006.
Samsung, “DDR2 Fully Buffered DIMM: 240pin FBDIMMs based on 512Mb C-die”.
Kennedy et al., “A 2Gb/s Point-to-Point Heterogeneous Voltage Capable DRAM for Capacity-Scalable Memory Subsystems”, IEEE International Solid-State Circuits Conference, 2004.
Kim et al., A 3.6Gb/s/pin Simultaneous Bidirectional (SBD) I/O Interface for High-Speed DRAM, IEEE International Solid-State Circuits Conference, 2004.
IEEE Standard for High-Bandwidth Memory Interface Based on Scalable Coherent Interface (SCI) Signaling Technology (RamLink), IEEE Std. 1596.4-1996, The Institute of Electrical Electronics Engineers, Inc., pp. i-91, (Mar. 1996).

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