Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2002-02-11
2003-04-01
Le, Don (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S093000, C331S1170FE
Reexamination Certificate
active
06542002
ABSTRACT:
Priority is claimed to Patent Application Number 2001-12245 filed in Rep. Of Korea on Mar. 9, 2001, herein incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a power supply circuit, and more particularly, to a hybrid power supply circuit combining a CMOS power supply portion to quickly charge/discharge a logic circuit and an adiabatic charging portion to minimize the power consumption during charging/discharging.
2. Description of the Related Art
Recently, the power consumption in digital circuits is under very intensive study since many electronic products have become mobile units which require low power consumption and long battery duration.
Most digital circuits are implemented with CMOS circuitry.
FIG. 1
shows a CMOS inverter circuit.
Referring to
FIG. 1
, an output voltage Vo can be a power voltage Vdd or grounded depending on an input voltage Vi. When the input Vi is a ground voltage GND (hereinafter will be referred as “low”), a transistor P turns on and a transistor N turns off. Accordingly, the current flows from power supply Vdd to an output capacitor C so as to be charged to the level of supply voltage Vdd (hereinafter will be referred as “high”). The other case, when the input voltage Vi is high, the transistor N turns on and the transistor P turns off. Accordingly, the current flows out from capacitor C to the ground so as to be discharged.
In case of above mentioned CMOS inverter circuit, capacitor C is charged or discharged in a short time in response to the input Vi and abruptly varied its voltage at an initial phase. So, the sudden variation in voltage during the charging/discharging results in a sudden increase of energy in the circuit and a heat dissipation in the transistors.
FIG. 2
shows an equivalent diagram of the inverter of
FIG. 1
during charging. Referring to
FIG. 2
, an electric charge Q is supplied to the capacitor C through a resistance R. The energy consumption E during the charging is calculated as follows:
E
=
E
supply
-
E
store
=
∫
V
dd
i
ⅆ
t
-
∫
v
c
i
ⅆ
t
=
1
2
C
V
d
d
2
[
Equation
1
]
Here, E
supply
is the energy being supplied, E
store
is the energy stored in capacitor C. That is, the energy E consumed during charging capacitor C is E
supply
less E
store
.
On the other hand, an adiabatic charging method can adjust the charging time by using a current source thereby minimizing the energy consumption.
FIG. 3
shows an equivalent diagram of the adiabatic charging circuit. Referring to
FIG. 3
, the energy consumption E during charging capacitor C is represented as follows:
E
=
∫
i
2
R
ⅆ
t
=
(
Q
t
)
2
R
t
=
R
t
(
C
V
d
d
)
2
=
R
C
t
C
V
d
d
2
[
Equation
2
]
As above, the energy consumption E can be obtained by integrating the square of current multiplied by resistance along time. Referring to Equation 2, the energy consumption E is proportional to the charging time t. At the extreme, when charging time goes to infinity, the energy can be supplied without heat dissipation. That is, to minimize the stream of the current (the velocity of charge), the collision to the resistance can be minimized. This implies that to avoid the sudden current changes as in CMOS circuit, an inductor can be used to control the current thereby minimizing the energy consumption.
FIG. 4
shows a power supply source using an inductor. Referring to
FIG. 4
, the charge to capacitor C and the discharge to inductor L are done depending on a resonance between capacitor and inductor so that energy needed is only the energy consumed during the charge/discharge.
Various methods to implement power source using the inductor have been proposed (U.S. Pat. No. 5,559,478). Most proposals use the resonance between the inductance and capacitance already fixed for deciding on charging or discharging speed of the circuit . In these cases, if the resonance frequency is used in deciding on the charging/discharging speed, the charging/discharging time and the resonance frequency are changed by changes in inductance and capacitance in the power supply circuit. The inductance and capacitance in the circuit may be changed by the circuitry making conditions such as temperature and processes therein, and also be changed by the operation of the circuit. In addition, to recharge the consumed energy, a switch S
2
in
FIG. 4
must be turned on. However, the switch control is not easy because of the varying charging/discharging time so that the commercial implementation of them is difficult.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a hybrid power supply circuit combining a CMOS power supply for quick charging/discharging a logic circuit and an adiabatic charging circuit for minimizing an energy consumption in charging/discharging.
Another object of the present invention is to provide a method for charging/discharging using the hybrid power supply circuit.
Still another object of the present invention is to provide a method for effectively charging/discharging a plurality of logic circuits which constitute a digital system by using the hybrid power supply circuit.
To achieve the first object of the invention, there is provided a power supply circuit for supplying a power to a logic circuit performing a digital logic process in response to an input signal and for controlling charging/discharging the logic circuit according to a process result, the power supply circuit comprising: an adiabatic power supply portion for charging/discharging the logic circuit in such a manner to suppress a sudden current change during a first predetermined time after the input signal changes; and a CMOS power supply portion for quickly charging/discharging the logic circuit to supply power level/ground level during a second predetermined time after the first predetermined time.
To achieve the second object of the invention, there is provided a method for charging/discharging a logic circuit performing a digital logic algorithm in response to an input signal by using a hybrid power supply circuit having an adiabatic power supply portion and a CMOS power supply portion, the method comprising the steps of: charging/discharging the logic circuit according to an output thereof by using the adiabatic power supply portion during a first predetermined time after the input signal changes; and charging/discharging the logic circuit to a required levels by using the CMOS power supply portion during a second predetermined time after the first predetermined time.
To achieve the third object of the invention, there is provided a method for charging/discharging a plurality of logic circuits in a digital system having the logic circuits operating synchronized to a system clock signal determined by a maximum delay time and a hybrid power supply circuit including an adiabatic power supply portion and a CMOS power supply portion for supplying a power to the logic circuits, the method comprising the steps of: (a) comparing all of the delay times of the logic circuits so as to determine the maximum delay time and comparing a delay time of a logic circuit to be charged/discharged with the maximum delay time; (b) charging/discharging the logic circuit to a required level by using the CMOS power supply portion if the delay time of the logic circuit is identical to the maximum delay time in step (a); (c) charging/discharging the logic circuit by using the adiabatic power supply portion during a first predetermined time if the delay time of the logical circuit is shorter than the maximum delay time in step (a); and (d) charging/discharging the logic circuit to a supply power level or a ground level after the first predetermined time.
REFERENCES:
patent: 5559463 (1996-09-01), Denker et al.
patent: 5559478 (1996-09-01), Ath
Jang Ho-rang
Jo Ki-won
Burns Doane , Swecker, Mathis LLP
Le Don
Samsung Electronics Co,. Ltd.
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