Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-09-09
2004-11-02
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C430S005000, C378S005000, C382S144000, C700S120000, C700S121000
Reexamination Certificate
active
06813759
ABSTRACT:
BACKGROUND
1. Field of the Invention
The invention relates to the process of designing an integrated circuit. More specifically, the invention relates to a method and an apparatus that facilitates a hybrid optical proximity correction technique for alternating phase shift masks.
2. Related Art
Recent advances in integrated circuit technology have largely been accomplished by decreasing the feature size of circuit elements on a semiconductor chip. As the feature size of these circuit elements continues to decrease, circuit designers are forced to deal with problems that arise as a consequence of the optical lithography process that is used to manufacture integrated circuits. This optical lithography process generally begins with the formation of a photoresist layer on the surface of a semiconductor wafer. A mask composed of opaque regions, which are generally formed of chrome, and light-transmissive clear regions, which are generally formed of quartz, is then positioned over this photoresist layer coated wafer. (Note that the term “mask” as used in this specification is meant to include the term “reticle.”) Light is then shone on the mask from a visible light source or an ultraviolet light source. More generally an appropriate type of electromagnetic radiation is used in combination with suitable masks and photoresists.
This light is generally reduced and focused through an optical system that contains a number of lenses, filters, and mirrors. The light passes through the clear regions of the mask and exposes the underlying photoresist layer. At the same time, the light is blocked by opaque regions of the mask, leaving underlying portions of the photoresist layer unexposed.
The exposed photoresist layer is then developed, typically through chemical removal of the exposed
on-exposed regions of the photoresist layer. The end result is a semiconductor wafer with a photoresist layer having a desired pattern. This pattern can then be used for etching underlying regions of the wafer.
One solution to producing ever-smaller feature sizes is to use phase shifting. In phase shifting, phase shifters are often incorporated into a mask in order to achieve line widths that are smaller than the wavelength of the light that is used to expose the photoresist layer through the mask. During phase shifting, destructive interference caused by two adjacent clear areas on a mask is used to create an unexposed area on the photoresist layer. This is accomplished by exploiting the fact that light passing through a mask's clear regions exhibits a wave characteristic having a phase that is a function of the distance the light travels through the mask material. By placing two clear areas adjacent to each other on the mask, one of thickness t
1
and the other of thickness t
2
, one can obtain a desired unexposed area on the underlying photoresist layer caused by interference. By varying the thickness t
1
and t
2
appropriately, the light exiting the material of thickness t
2
is 180 degrees out of phase with the light exiting the material of thickness t
1
. Phase shifting is described in more detail in U.S. Pat. No. 5,858,580, entitled “Phase Shifting Circuit Manufacture Method and Apparatus,” by inventors Yao-Ting Wang and Yagyensh C. Pati, filed Sep. 17, 1997 and issued Jan. 12, 1999, which is hereby incorporated by reference.
There can be problems with existing phase shifting techniques and the ability to use standard optical proximity correction (OPC) techniques to bring the predicted feature width to the desired feature width. As shown in
FIG. 1
, the nominal line width (critical dimension) varies with &sgr; (or partial coherency) over different pitches. More specifically, a small &sgr; provides higher resolution and better process windows but exhibits worse proximity effects. Thus, for example if the target critical dimension (CD) is 70 nm, then, the range of variation in CD through pitch is too large to be corrected with current OPC techniques.
Another problem arises during the process of generating phase shifters and associated trim for the complementary mask. A phase shifter located on a phase shifting mask is generated along with associated trim located on a complementary mask. During exposure of the complementary mask, this trim protects the region left unexposed by the phase shifter during exposure of the phase shifting mask. Attempts have been made to apply trim correction on small trim widths. However, applying trim correction to small trim widths leads to a number of problems: it can reduce image contrast; it can reduce the size of the process window; and it can reduce the overlay budget. Hence, applying trim correction to small trim widths is generally unacceptable as a manufacturing solution. Optical proximity correction for trim masks is performed only on edges that were in the original layout.
What is needed is a method and an apparatus for adjusting trim without the problems stated above.
SUMMARY
One embodiment of the invention provides a system that facilitates optical proximity correction for alternating phase shift masks. During operation, the system receives a layout, which includes a complementary mask and a phase shift mask. Next, the system performs a first optical proximity correction process on the complementary mask. This first optical proximity correction process adjusts a subset of features within a given pitch range on the complementary mask. The system then performs a second optical proximity correction process on the phase shift mask for PSM defined features. This second optical proximity correction process adjusts a phase shifter width on the phase shift mask.
In one embodiment of the invention, the first optical proximity correction process involves a, simple, rule-based optical proximity correction process.
In one embodiment of the invention, the second optical proximity correction process involves a model-based optical proximity correction process. In an alternative embodiment, a rule based optical proximity correction process can be used.
In one embodiment of the invention, adjusting a feature on the complementary mask involves moving a distal trim edge relative to an associated gate structure.
In one embodiment of the invention, adjusting the phase shifter width involves moving either a shifter edge or a chrome regulator edge of a phase shifter.
Although the term “optical proximity correction” is used, more generally the correction can be for all types of proximity effects such as microloading effects, etc., to the extent the rules and models have been designed with such proximity effects in mind.
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Choi, Y., et al., “Optical Proximity Correction on Attenuated Phase Shifting Photo Mask for Dense Contact Array”, LG Semicon Company (11 pages), no date.
Toublan, O., et al., “Phase and Transmission Errors Aware OPC Solution for PSM: Feasibility Demonstration”, Mentor Graphics Corp. (7 pages), no date.
Rieger, M., et al., “System for Lithography Proximity Compensation”, Precim Company, Portland, Oregon, Sep. 1993 (28 pages).
Ohnuma, H., et al., “Lithography Computer Aided Design Technology for Embedded Memory in Logic”, Jpn. J. Appl. Phys. vol. 37, Part I, No. 12B, pp. 6686-6688, Dec. 1998.
Spence, C., et al., “Integration of Optical Proximity Correction Strategies in Strong phase Shifters Design for Poly-Gate Layers”, Bacus News, vol. 15, Issue
Lai Weinong
Li Xiaoyang
Liu Hua-yu
Kik Phallaka
Numerical Technologies Inc.
Park Vaughan & Fleming LLP
Smith Matthew
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