Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-05-03
2011-05-03
Ngo, Ngan (Department: 2893)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S261000, C438S265000, C438S287000, C257SE29309, C257SE21423
Reexamination Certificate
active
07935596
ABSTRACT:
Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.
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Cheng Ning
Choi Ji-hwan
Kinoshita Hiro
Wu Huaqiang
Ngo Ngan
Spansion LLC
Turocy & Watson LLP
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