Hot-plug of PCI bus using single chip

Details Hot-plug of PCI bus using single chip Hot-plug of PCI bus using single chip

1998-07-31

2001-06-26

Beausoleil, Robert (Department: 2781)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

Reexamination Certificate

active

06253267

ABSTRACT:

CLAIM OF PRIORITY
This application makes reference to, incorporates the same herein, and claims all benefits accruing, under 35 U.S.C §119 from an application entitled A Hot-Plug Of PCI Bus Using Single Chip earlier filed in the Korean Industrial Property Office on Jul. 31, 1997, and there duly assigned Serial No. 97-36523 by that Office.
1. Field of the Invention
The present invention relates to a hot-plug controller of a PCI (Peripheral Component Interconnect) bus using a single chip, and more particularly, to a method for implementing all functions necessary for the PCI hot-plug on a single chip.
2. Description of the Related Art
A prior method for implementing the PCI hot-plug needs the functions of: controlling power ON/OFF for each PCI slot; controlling independently to RST# of each PCI slot; controlling independently to attention indicator of each PCI slot; monitoring the equipment of an adapter card for each PCI slot; confining the performance of 66 Mhz for the main PCI bus and slot; performing the physical identification for each PCI slot; supplying only the present slot with power (not shutting off the present slot); interfacing with PCI, USB and I2C busses; and isolating a signal of each PCI slot.
The apparatus for power on-off is known to include Harris Semiconductor's HIP 1011 and Motorola's MC33XXX. And a signal isolation device has 24-bits, and three 32-bit PCI buses are needed per slot. Also, a controller is needed to control all the data as 32-bits plus a control bit or more by interfacing with the system.
A problem of the prior art is that at least five devices are needed. In addition, the prior art has problems such as available area on a printed circuit board, high costs, low reliability, etc.
In general, when a fault occurs in the computer peripheral devices, it is settled while the power is off for the whole system. And the system-down time contributes to a great cost and is an inconvenience to a computer-user. For solving the problems, a large number of vendors have given out the methods for a PCI Hot-Plug Specification. However, for implementing various functions, a lot of discrete components have been needed.
Examples of known devices for enabling hot plugging are found in U.S. Pat. No. 5,781,744 to Mary B. Johnson et al. entitled Method And Apparattus For Ensuring Safe Peripheral Connection; U.S. Pat. No. 5,712,754 to Chi Kim Sides et al. entitled Hot Plug Protection System; and U.S. Pat. No. 5,272,584 to Pierre Austruy et al. entitled Hot-Plugging Circuit For The Interconnection Of Cards To Boards.
SUMMARY OF THE INVENTION
For solving the prior art problems, the present invention is intended to provide a hot-plug controller of a PCI (Peripheral Components Interconnects) bus using a single chip, and more specifically, to provide a method for designing the controller of a PCI hot-plug to reduce the costs and increase reliability by implementing all functions for the PCI hot-plug on a single chip. Hereafter, “single chip” means one of a Field Programmable Gate-Array (FPGA), Application Specific Integrated Circuit (ASIC), and Hybride circuit.
A PCI hot-plug controller using FPGA and ASIC implements all functions necessary for the PCI hot-plug on a single chip, the PCI hot-plug controller includes: a system interface unit transmitting data via a PCI, USB and I2C bus; a register unit, which is connected to the system interface unit, and receives a reset control signal, a present detection signal, enable signal, LED (light emitting diode) control signal and physical identification (ID) signal from the outside, and stores the signals; a power control unit reading data from the register unit and outputting a signal to control the system power and slot power; and a bus isolation unit reading the control signal from the register unit and making the signal-line between the PCI bus signal and PCI slot ON/OFF.
The present invention provides design technology to reduce costs and increase reliability by implementing the above-mentioned functions on single chip.


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