Electrical computers and digital data processing systems: input/ – Input/output data processing – Concurrent input/output processing and data transfer
Reexamination Certificate
1998-06-02
2001-03-13
An, Meng-Ai T. (Department: 2183)
Electrical computers and digital data processing systems: input/
Input/output data processing
Concurrent input/output processing and data transfer
C710S001000, C710S021000, C710S052000
Reexamination Certificate
active
06202105
ABSTRACT:
CROSS-REFERENCE TO THE ATTACHED APPENDICES
Appendices A-F, which are part of the present disclosure, are included in a microfiche appendix consisting of 19 sheets of microfiche having a total of 1036 frames, and the microfiche appendix is incorporated herein by reference in its entirety. Microfiche Appendices A-C are listings of computer programs and related data including source code in the language VERILOG for implementing a “receive payload buffer and manager” for use with one embodiment of this invention as described more completely below. Microfiche Appendices D-F are a listing of documentation for the computer programs of Microfiche Appendices A-C. Appendix G is a paper appendix consisting of ten pages attached hereto, and is a listing of computer progams of the type described above in reference to Appendices A-C.
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is related to and incorporates by reference herein in their entirety, the following copending, concurrently filed, commonly owned U.S. Patent Applications:
(1) Ser. No. 09/089/030 entitled “A Host Adapter Having A Snapshot Mechanism,” by Salil Suri Taikhim Henry Tan;
(2) Ser. No. 09/089,044, entitled “Multiple Access Memory Architecture” by Stillman Gates and Uday N. Devanagundy;
(3) Ser. No. 09/089,057, entitled “Decoupled Serial Memory Access with Passkey Protected Memory Areas” by Uday N. Devanagundy et al;
(4) Ser. No. 09/088,812, entitled “Source-Destination Re-Timed Cooperative Communication Bus” by Stillman Gates.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related generally to a host adapter for transferring information between a first bus inside a personal computer (also called “computer bus”) and a second bus to which one or more peripheral devices (such as disk drives) are connected (also called “peripheral bus”), and in particular to a circuit that transfers to the computer bus data that was previously received from the peripheral bus and vice versa.
2. Description of the Related Art
A personal computer
90
(
FIG. 1A
) includes a plug-in board
10
that is coupled to two buses namely (1) a computer bus (such as the ISA/EISA bus well known in the art)
20
on a mother board
60
and (2) a peripheral bus (e.g. SCSI bus also well known in the art)
40
. Peripheral bus
40
is, in turn, connected to one or more peripheral devices, e.g. devices
31
and
32
. Similarly, computer bus
20
is coupled to one or more devices on board
60
, such as system memory
64
, and to a local bus
65
that in turn is coupled to a host processor
61
(e.g. the microprocessor PENTIUM available from Intel Corporation, Santa Clara, Calif.). Local bus
65
is also coupled to a read only memory (also called “processor ROM”)
62
that holds software, e.g. Basic Input-Output System (BIOS) instructions to be executed by processor
61
on power up. Moreover, plug-in board
10
also includes a read only memory
11
that is programmed with instructions to be executed by host adapter
12
on power up. Instead of being mounted on a separate board
10
, host adapter
12
and read only memory
11
can be mounted directly on a mother board
70
(FIG.
1
B).
Peripheral bus
40
may conform to the specification of the Small Computer System Interface (SCSI) standard available from the American National Standards Institute (ANSI x3.131-1986) of 1430 Broadway, New York, N.Y. 10018. The just-described SCSI standard specification is incorporated by reference herein in its entirety. Additional descriptions related to the SCSI bus may be found in, for example, U.S. Pat. Nos. 4,864,291 and 4,905,184 that are both incorporated by reference herein in their entirety.
Computer bus
20
may conform to any of the computer bus standards, such as the Industry Standard Architecture (ISA), Extended ISA (EISA), or Peripheral Component Interconnect (PCI). The PCI specification is available from PCI Special Interest Group (SIG), MIS HF3-15A, 5200 NE Elam Young Parkway, Hillsborough, Oreg. 97124-6497, phone number 503/696-2000, and is incorporated by reference herein in its entirety. Additional descriptions related to the PCI bus can be found in the book “PCI System Architecture”, Second Edition, by Tom Shanley and Don Anderson, MindShare Press, Richardson, Texas, 1994 also incorporated by reference herein in its entirety.
Computer bus
20
is typically faster than peripheral bus
40
, and therefore a conventional host adapter
12
(as described in, for example, U.S. Pat. No. 5,659,690 by Stuber et al that is incorporated by reference herein in its entirety) has a FIFO buffer to collect data from peripheral bus
40
, and transfer the collected data in a burst mode over computer bus
20
. Host adapter
12
can transfer the data from a peripheral device
31
directly to system memory
64
, without intervention of host processor
61
, in a mechanism known as “Direct Memory Access” (DMA), as described by Stuber et al at column 90, line 38 et seq.
The data transfer described above can be initiated by transferring to host adapter
12
a command in the form of a “Sequencer Control Block” (SCB) that contains information needed by host adapter
12
to perform the data transfer, as described by Stuber et al. at column 17, line 66 et. seq. Moreover, host adapter
12
can transfer the data to/from system memory
64
via a scatter/gather mechanism that stores the data in a number of portions in system memory
64
. The SCB includes “a pointer to a scatter/gather data transfer pointer list, [and] a count of the number of elements in the scatter/gather lists” (column 18, lines 3-5) that together indicate the portions of system memory
64
(
FIG. 1A
) to or from which the data is to be transferred.
Host adapter
12
typically has more than one SCSI command pending in a queue of SCBs as described by Stuber et al. at column 20, line 1 et seq. In one example, SCBs for each of two peripheral devices
31
and
32
are queued, and when a first peripheral device
31
disconnects from host adapter
12
(e.g. while the drive mechanics are repositioned) host adapter
12
communicates with a second peripheral device
32
to execute an SCSI command indicated by the another SCB.
The ability of host adapter
12
to switch back and forth between SCBs, is referred to as “context switching” (Stuber et al., column 20, line 9). During a context switch (e.g. when a data transfer is suspended or is completed), a new data transfer is not started until the above-described FIFO buffer in host adapter
12
(that was used to collect data from peripheral bus
40
) is emptied. [Depending on the size of the FIFO buffer, peripheral bus
40
may remain idle for a significant duration, e.g. several microseconds.]
SUMMARY OF THE INVENTION
A host adapter in accordance with the invention includes a first circuit (hereinafter “receive data path”) that receives data from a peripheral bus (that is coupled to a peripheral device) and transfers the received data to a computer bus (that is located inside a personal computer). The host adapter also includes a second circuit (hereinafter “send data path”) that transfers data in the opposite direction, specifically from the computer bus to the peripheral bus. The rate of receipt of data by the host adapter from the peripheral bus is smaller than the rate of transfer of data from the host adapter to the computer bus. Therefore, each of the receive data path and the transmit data path includes a buffer (formed of storage elements) for temporarily holding the data being transferred. The host adapter uses each of the two buffers for storing only the data being transferred in the respective direction, each independent of the other, for full-duplex dat
Gates Stillman F.
Suri Salil
Adaptec, Inc.
An Meng-Ai T.
Skjerven Morrill & MacPherson LLP
Suryadevara Omkar K.
Whitmore Stacy
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