Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-01-04
2005-01-04
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000
Reexamination Certificate
active
06838726
ABSTRACT:
Structures and methods for memory devices are provided which operate with lower control gate voltages than conventional floating gate transistors, and which do not increase the costs or complexity of the device fabrication process. In one embodiment of the present invention, the novel memory cell includes a source region and a drain region separated by a channel region in a horizontal substrate. A first vertical gate is separated from a first portion of the channel region by a first oxide thickness. A second vertical gate is separated from a second portion of the channel region by a second oxide thickness. According to the teachings of the present invention, the total capacitance of these memory devices is about the same as that for the prior art of comparable source and drain spacings. However, according to the teachings of the present invention, the floating gate capacitance (CFG) is much smaller than the control gate capacitance (CCG) such that the majority of any voltage applied to the control gate will appear across the floating gate thin tunnel oxide.
REFERENCES:
patent: 4051354 (1977-09-01), Choate
patent: 5327380 (1994-07-01), Kersh, III et al.
patent: 5386132 (1995-01-01), Wong
patent: 5583360 (1996-12-01), Roth et al.
patent: 5625213 (1997-04-01), Hong
patent: 5661055 (1997-08-01), Hsu et al.
patent: 5793080 (1998-08-01), Hwang
patent: 5847425 (1998-12-01), Yuan et al.
patent: 5910912 (1999-06-01), Hsu
patent: 5991225 (1999-11-01), Forbes et al.
patent: 6078076 (2000-06-01), Lin
patent: 6093945 (2000-07-01), Yang
patent: 6124729 (2000-09-01), Noble et al.
patent: 6133601 (2000-10-01), Watanabe
patent: 6208164 (2001-03-01), Noble et al.
patent: 6219299 (2001-04-01), Forbes et al.
patent: 6222788 (2001-04-01), Forbes et al.
patent: 6377070 (2002-04-01), Forbes
Horiguchi et al.,IEDMA direct Tunneling . . . Structure pp 922-924, Dec. 1999.*
“Frequently-Asked Questions (FAQ) About Programmable Logic”,OptiMagic, Inc., http://www.optimagic.com/faq.html, pp. 1-18, (1997).
Chen, W., et al., “Very uniform and high aspect ratio anisotrophy SIO2 etching process in magnetic neutral loop discharge plasma”,J. Vac. Sci. Technol. A, 17(5), pp. 2546-2550, (1999).
Dipert, B., et al., “Flash Memory Goes Mainstream”,IEEE Spectrum, 30, 48-52, (Oct. 1993).
Hodges, D.A., et al.,Analysis and Design of Digital Integrated Circuits, McGraw-Hill Book Company, 2nd Edition, 394-396, (1988).
Hodges, D.A., et al.,Analysis and Design of Digital Integrated Circuits, 2nd Edition, McGraw-Hill Publishing. New York, pp. 354-357, (1988).
Johnson, J., et al., “IBM's 0.5 micrometer Embedded Flash Memory Technology”,MicroNews, 4(3), http://www.chips.ibm.com/micronews/vol14_no3/flash.html, pp. 1-7, (1998).
Landheer, D., et al., “Formation of high-quality silicon dioxide films by electron cyclotron resonance plasma oxidation and plasma-enhanced chemical vapour deposition”,Thin Solid Films, 293, pp. 52-62, (1997).
Moore, W.R., “A Review of Fault-Tolerant Techniques for the Enhancement of Integrated Ccircuit Yield”,Proceedings fo the IEEE, 74(5), 684-698, (May 1986).
Nozawa, R., et al., “Low temperature polycrystalline silicon film formation with and without charged species in an electron cyclotron resonance SiH4/H2 plasma-enhanced chemical vapor deposition”,J. Vac. Sci. Technol. A, 17(5), pp. 2542-2545, (1999).
Patel, P., et al., “Low temperature VUV enhanced growth of thin silicon dioxide films”,Applied Surface Science, 46, pp. 352-356, (1990).
Rueger, N.R., et al., “Selective etching of SiO2 over polycrystalline silicon using CHF3 in an inductively coupled plasma”,J. Vac. Sci. Technol. A, 17(5), pp. 2492-2502, (1999).
Shindo, W., et al., “Low-temperature large-grain poly-Si direct deposition by microwave plasma enhanced chemical vapor disposition using SiH4/Xe”,J. Vac. Sci. Technol. A, 17(5), pp. 3134-3138, (1999).
Usami, K., et al., “Thin Si Oxide films for MIS tunnel emitter by hollow cathode enhanced plasma”,Thin Films, 281-282, pp. 412-414, (1996).
Vallon, S., et al., “Polysilicon-germanium gate patterning studies in a high density plasma helicon source”,J. Vac. Sci. Technol. A, 15(4), pp. 1874-1880, (1997).
Ahn Kie Y.
Forbes Leonard
Jackson Jerome
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
LandOfFree
Horizontal memory devices with vertical gates does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Horizontal memory devices with vertical gates, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Horizontal memory devices with vertical gates will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3403446