Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – By reaction with substrate
Reexamination Certificate
2011-01-11
2011-01-11
Garber, Charles D (Department: 2812)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
By reaction with substrate
C438S099000, C438S149000, C438S750000, C438S758000, C438S779000, C257SE21015, C257SE21017, C257SE21018, C257SE21021, C257SE21269
Reexamination Certificate
active
07867916
ABSTRACT:
A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.
REFERENCES:
patent: 7331218 (2008-02-01), Trainoff
patent: 7776709 (2010-08-01), Colburn et al.
patent: 2009/0047423 (2009-02-01), Robinson
Deegan et al.: “Contact Line Deposits in an Evaporating Drop”, Physical Review E, vol. 62, No. 1, Jul. 2000, pp. 756-765.
Arias Ana Claudia
Sambandan Sanjiv
Street Robert A.
Ahmadi Mohsen
Bever Patrick T.
Bever Hoffman & Harms LLP
Garber Charles D
Palo Alto Research Center Incorporated
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