Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-12-27
2010-11-23
Blum, David S (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S425000, C257SE21409, C257SE21545, C257SE23002, C257SE29255
Reexamination Certificate
active
07838370
ABSTRACT:
A method for manufacturing an isolation structure is disclosed that protects the isolation structure during etching of a dichlorosilane (DCS) nitride layer. The method involves the formation of a bis-(t-butylamino)silane-based nitride liner layer within the isolation trench, which exhibits a five-fold greater resistance to nitride etching solutions as compared with DCS nitride, thereby allowing protection against damage from unintended over-etching. The bis-(t-butylamino)silane-based nitride layer also exerts a greater tensile strain on moat regions that results in heightened carrier mobility of active regions, thereby increasing the performance of NMOS transistors embedded therein.
REFERENCES:
patent: 5677231 (1997-10-01), Maniar et al.
Bather Wayne Anthony
Mehta Narendra Singh
Varghese Ajith
Blum David S
Brady III Wade J.
Franz Warren L.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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