Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-01-23
1999-12-14
Wortman, Donna C.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438700, 438729, 438743, C03C 1500
Patent
active
06001699&
ABSTRACT:
A method for forming contacts with vertical sidewalls, high aspect ratios, improved salicide and photoresist etch selectivity at submicron dimensions. In one currently preferred embodiment, an opening is formed in a dual oxide layer by etching the undoped oxide layer at a first rate and then etching the doped oxide layer at a second rate. The etch process is performed in a low density parallel plate reactor. The process parameters of the etch are fixed in ranges which optimize the etch process and allow greater control over the critical dimensions of the opening. For example, the oxide layer is etched at a pressure in the range of approximately 100-300 mTorr and with an etch chemistry having a CHF.sub.3 :CF.sub.4 gas flow ratio in the range of approximately 3:1-1:1, respectively.
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Solid State Technology, Penwell Publishing Co., vol. 38, No. 12, Dec. '95, p. 108.
Fradkin Mark A.
Nguyen Phi L.
Vandentop Gilroy J.
Brumback Brenda G.
Intel Corporation
Wortman Donna C.
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