Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-06-19
2000-07-11
Booth, Richard
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
257316, 438527, H01L 218247
Patent
active
060872195
ABSTRACT:
A method of forming a Flash EEPROM device with a gate electrode stack includes forming a a tunnel oxide layer, a floating gate electrode layer, a dielectric layer, and a control gate layer on a doped silicon semiconductor substrate. Then form source/drain regions in the substrate. Next, form a surface P+ doped halo region in the surface of the N+ source region juxtaposed with the control gate electrode. The P+ halo region is surrounded by the N+ source region. The result is a device which is erased by placing a negative voltage of about -10V on the control gate and a positive voltage of about 5V on the combined source region/halo region to produce accumulation of holes in the channel which distributes the flow of electrons into the channel rather than concentrating the electrons near the interface between the source region and the edge of the tunnel oxide layer. The tunnel oxide layer has a thickness from about 70 .ANG. to about 120 .ANG..
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Chung Steve S.
Hsu Ching-Hsiang
Liang Mong-Song
Ackerman Stephen B.
Booth Richard
Jones, III Graham S.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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