Highly integrated low voltage SRAM array with low resistance Vss

Details Highly integrated low voltage SRAM array with low resistance Vss Highly integrated low voltage SRAM array with low resistance Vss

1997-02-05

1998-11-03

Meier, Stephen

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

H01L 2976, H01L 2994, H01L 31062, H01L 31113

Patent

active

058313150

ABSTRACT:
An SRAM array configuration is disclosed. SRAM cells (102) are arranged in rows and columns. Cell rows (104a-104f) are each driven by a particular word line (132). Cell row pairs (108a and 108b) are supplied with a low power supply voltage (Vss) by a number of Vss connections 116 disposed parallel to the cell rows (104a-104f). The word lines (132) and Vss connections 116 are "strapped" by low resistance word line straps (110b-110e) and Vss straps (112a-112b). Both the word line straps (110b-110e) and the Vss straps (112a-112b) are substantially offset with respect to their associated word lines (132) and Vss connections 116, respectively. The Vss strap offset is accomplished with the use of a Vss line 140 that makes contact with the Vss connections 116 and further includes landing portions 120 which extend in the column direction and make contact with the Vss straps (112a-112b).

REFERENCES:
patent: 4125854 (1978-11-01), McKenny et al.
patent: 4554644 (1985-11-01), Chen et al.
patent: 4631705 (1986-12-01), Honda
patent: 5005068 (1991-04-01), Ikeda et al.
patent: 5483083 (1996-01-01), Meguro et al.
patent: 5521860 (1996-05-01), Ohkubo

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