Higher voltage drain extended MOS transistors with...

Details Higher voltage drain extended MOS transistors with... Higher voltage drain extended MOS transistors with...

2001-09-14

2003-12-09

Chaudhuri, Olik (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S303000, C438S306000, C438S301000, C438S302000

Reexamination Certificate

active

06660603

ABSTRACT:

FIELD OF THE INVENTION
The invention is generally related to the field of MOSFET transistors and more specifically to an integrated high voltage drain extended transistor.
BACKGROUND OF THE INVENTION
In integrated circuits there is often the need to have a number of different operating voltages. Circuits that use transistors with gate lengths less than 0.25 um typically operate at voltages less than 2.5 volts. For input-output operations (i.e., connection to circuits external to the chip) longer gate length transistors (>0.3 um) typically operate at about 2.5V to 3.3V. In some instances such as disk drive controllers, the circuits might require a 5 volt signal. In these cases, transistors capable of operating at high voltages are required. A transistor suitable for use at high voltages in integrated circuits is a drain extended (DE) transistor. Drain extended transistors may also be used in applications where the voltage on the drain exceeds the normal voltage rating of the gate oxide. Drain extended transistors differ from regular self aligned polysilicon gate transistors in that they use a very lightly doped extension region adjacent to the drain that depletes at high drain voltages. This allows much of voltage to be dropped across the silicon, reducing the electric field across the gate oxide to a safe level. Drain extended transistors allow operation at several times the rated voltage of core transistors, can handle analog signals of several volts, are suitable for power amplifiers and power conditioning circuits, and are generally more robust than conventional transistors having the same thickness of gate oxide. In particular, it is not necessary to add extra drain implants to control channel hot carrier (CHC) effects, and the higher breakdown voltage simplifies electrostatic discharge (ESD) protection; for example it is not normally necessary to include the resistors commonly required in series with application specific integrated circuits (ASIC) outputs.
Typically, to incorporate DE transistors into a CMOS integrated circuit, additional and special processes are required. These processes usually add cost and complexity to producing the integrated circuit. In the instant invention, DE transistor structures and processing methods are described that allow the incorporation of high voltage DE transistors into integrated circuits without introducing added processing complexity. In addition, DE transistors typically have a long channel length to avoid short channel effects and low BVdss when the polysilicon gate is mis-aligned or the polysilicon gate does not properly overlap the well structures in the substrate. The instant invention describes a double self-aligned process the allows DE transistors to fabricated with channel lengths on the order of the critical photolithography dimensions.
SUMMARY OF THE INVENTION
The integrated DE transistor structures described herein according to the instant invention can be fabricated using technology suitable for fabricating MOS transistors with sub micron gate lengths. In particular, a method for forming a drain extension transistor comprises the following: providing a semiconductor substrate with a plurality of isolation structures and a first well region of a first conductivity type; forming a masking layer on a first area of said first well region; implanting said first well region to form regions of a second conductivity type in said first well region adjacent to said masking layer; removing said masking region; forming a gate dielectric on said first well region; forming a gate layer on said gate dielectric; patterning said gate layer to form a gate structure and drain alignment structures such that said gate structure overlies a portion of said first well region and a portion of said regions of said second conductivity type; forming a patterned film to mask an area between said gate structure and said drain alignment structures; and simultaneously forming a source region and a drain region in said regions of said second conductivity type.
In addition to the above described method the plurality of isolation structures are LOCOS or STI. The masking layer comprises photoresist and the gate dielectric comprises a material selected from the group consisting of an oxide, thermally grown SiO2, a nitride, an oxynitride, a silicate, and any combination thereof.


REFERENCES:
patent: 5747850 (1998-05-01), Mei
patent: 5903032 (1999-05-01), Duvvury
patent: 6071768 (2000-06-01), Duvvury et al.
patent: 6096609 (2000-08-01), Kim et al.
patent: 6100125 (2000-08-01), Hulfachor et al.

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