High voltage transistor scaling tilt ion implant method

Details High voltage transistor scaling tilt ion implant method High voltage transistor scaling tilt ion implant method

2006-03-14

2006-03-14

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S217000, C257S335000

Reexamination Certificate

active

07011998

ABSTRACT:
The present invention is a high voltage transistor formation method and system that includes a varying or gradient concentration lightly doped drain and source implant region. The lightly doped drain (LDD) implant region has gradient concentration characteristics that provide a higher concentration under a source and drain and lower concentration close to a surface source drain channel formation under a gate. A lightly doped drain tilt implant process is utilized to form a component area (e.g., a transistor source and/or drain area) with gradient doping profiles. The varying concentration profile provides a smooth electrical characteristic transformation between regions that reduces the probability of hot electron generation otherwise associated with electrical fields that cross abrupt changes between different conductivity orientation regions. The higher concentration of the light dopants at the bottom of the source and drain regions also helps reduce the probability of deep junction breakdown.

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