Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-07-23
1998-11-17
Niebling, John
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438942, 438945, H01L 218238
Patent
active
058375716
ABSTRACT:
This invention relates to methodology to resolve the problem of low drain/source breakdown voltage (BVdss) in small geometry devices with thin gate oxide. Improved drain diffusion profile implanting through disjoint NSD/NWELL windows in the extended drain region, This provides essentially an improved lightly diffused (LDD) structure. Further this invention relates to alternative methods to resolve the problem of low drain/source breakdown voltage in other structures which can be achieved by for example, building a number of side wall oxide layers, impurity compensation or oxygen implantation. The improved LDD structure to which this invention relates has a number of advantages when compared with other solutions. It enables high voltage transistors to be fabricated with high drive capability, without additional process steps being required to implement the structure. The inventions will find applications wherever a high voltage capability is required to interface with the outside world. Such designs would include automotive applications; programming transistors for Field Programmable Gate Arrays; Robust I/O's and ESD Protection Circuits.
REFERENCES:
patent: 3951694 (1976-04-01), Monfret
patent: 4371403 (1983-02-01), Ikubo et al.
patent: 4722909 (1988-02-01), Parrillo et al.
patent: 5183771 (1993-02-01), Mitsui et al.
patent: 5200352 (1993-04-01), Pfiester
patent: 5424234 (1995-06-01), Kwon
patent: 5480746 (1996-01-01), Jinbo et al.
patent: 5604059 (1997-02-01), Imura et al.
patent: 5635316 (1997-06-01), Dao
Donaldson Richard L.
Kempler William B.
Lebentritt Michael S.
Niebling John
Texas Instruments Incorporated
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