Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Patent
1988-03-25
1990-01-09
Gossage, Glenn A.
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
365185, 36523006, 365226, 323313, 323317, 3072966, G11C 700, G05F 316, H03K 301
Patent
active
048932752
ABSTRACT:
A nonvolatile semiconductor memory device includes a power voltage select circuit that is comprised of first and second power source nodes, an output node, first and second depletion type MOS transistors connected in series between the first power source node and the output node, a third MOS transistor connected between an interconnection point between the first and second depletion type MOS transistors and the second power source node, and a fourth MOS transistor connected between the second power source node and the output node.
REFERENCES:
patent: 4365316 (1982-12-01), Iwahashi et al.
patent: 4368524 (1983-01-01), Nakamura et al.
patent: 4565932 (1986-01-01), Kuo et al.
patent: 4733371 (1988-03-01), Terada et al.
Carr et al., "Mos ILSI Design and Application", McGraw-Hill Book Company, New York, pub. 1972, pp. 42-49.
Atsumi et al., "Fast Programmable 256K ROM With On-Chip Test Circuits", IEEE Jour. of Solid State Circuits, vol. SC-20, No. 1, Feb. 1985, pp. 422-427.
Atsumi Shigeru
Imamiya Keniti
Ohtsuka Nobuaki
Tanaka Sumio
Gossage Glenn A.
Kabushiki Kaisha Toshiba
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