High voltage output stage for driving an electric load

Details High voltage output stage for driving an electric load High voltage output stage for driving an electric load

1998-10-30

2001-02-06

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S068000, C326S081000

Reexamination Certificate

active

06184716

ABSTRACT:

TECHNICAL FIELD
This invention relates to a high-voltage final output stage for driving an electric load.
More particularly, the invention relates to a high-voltage final output stage for driving an electric load, of the type which comprises a complementary pair of transistors connected between first and second supply voltage references, and including at least one PMOS pull-up transistor connected in series with an NMOS pull-down transistor.
BACKGROUND OF THE INVENTION
As is well known, a final output stage of a generic electronic circuit basically includes a drive portion intended for powering a load. Thus, the output stage should be capable of draining or taking up current from the load, according to necessity and the type of application involved.
Countless configurations have been provided in the prior art for the output stage.
FIG. 1
attached hereto shows schematically one of the most common such output stage configurations.
The output stage in
FIG. 1
comprises a complementary pair of MOS transistors connected in series with each other, between a first voltage reference Vdd and a second voltage reference Vss, wherein the latter may either be a negative supply or a ground.
Complementary pairs of MOS transistors are mostly employed in output stages on account of the definite advantages that they afford as regards the control logics, however, the considerations made herein below would also apply to output stage configurations incorporating bipolar transistors or any other pairs of MOS transistors.
The first transistor M
7
in the complementary pair is a pull-down transistor of either the NMOS or the DMOS type, and has its body terminal connected to its source terminal.
The second transistor M
8
in the complementary pair is a pull-up transistor of the thin oxide PMOS type, and has its body terminal connected to its source terminal.
The transistors M
8
and M
7
are connected to each other through their respective drain terminals, which terminals coincide with an output node OUT. An electric load, not shown, is connected between this output node OUT and ground.
The electric load is driven alternately by the PMOS transistor M
8
or the NMOS transistor M
7
, according to the different sourcing or of sinking operation modes.
Respective driver circuits have their respective outputs connected to the gate terminals of the transistors M
8
and M
7
.
FIG. 1
shows, by way of example, a level shifter circuit for driving the transistors M
7
and M
8
of the final output stage thereby transferring an information from a low-voltage signal to a high-voltage signal. The circuit shown includes two NMOS drive transistors M
1
and M
2
, two PMOS buffer transistors M
4
and M
3
effecting the voltage shift, and two additional PMOS transistors MS and M
6
forming a bistable flip-flop for storing information about the state of the power PMOS M
8
. The gate terminal of the output PMOS M
8
is connected to one, M
3
, of the two PMOS buffer transistors.
A shifter circuit of this kind also requires a reference voltage, to be obtained through a few zeners, for example, for biasing the gate terminals of the MOS buffer transistors M
3
and M
4
.
SUMMARY OF THE INVENTION
For many applications, output stages which can operate in both low-voltage and high-voltage conditions would be desirable.
However, the prior art offers no solutions which can efficiently fill the demand in terms of performance as well as of reduced occupation of circuit area.
An embodiment of this invention provides an output stage and associated level shifting driver circuit which have such respective functional and structural features as to be usable in low-driving and high-driving voltage applications and occupy a reduced circuit area.
The embodiment provides an output stage which incorporates both a thin oxide PMOS transistor and a thick oxide PMOS transistor, and has both transistors driven from the same level shifting driver circuit.
Based on this solving idea, the technical problem is solved by a final output stage as previously indicated and defined in the characterizing portion of claim
1
.
Features and advantages of the circuit according to this invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.


REFERENCES:
patent: 5128555 (1992-07-01), Millman
patent: 5142244 (1992-08-01), Glica et al.
patent: 5583454 (1996-12-01), Hawkins et al.
patent: 5815013 (1998-09-01), Johnston

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