High voltage MOS transistor with up-retro well by providing...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S294000, C438S220000

Reexamination Certificate

active

06989309

ABSTRACT:
A high voltage MOS transistor is provided that is compatible with low-voltage, sub-micron CMOS and BiCMOS processes. The high voltage transistor of the present invention has dopants that are implanted into the substrate prior to formation of the epitaxial layer. The implanted dopants diffuse into the epitaxial layer from the substrate during the formation of the epitaxial layer and subsequent heating steps. The implanted dopants increase the doping concentration in a lower portion of the epitaxial layer. The implanted dopants may diffuse father into the epitaxial layer than dopants in the buried layer forming an up-retro well that prevents vertical punch-through at high operating voltages for thin epitaxial layers. Particularly, a P-type dopant may diffuse farther up into an epitaxial layer than an N-type dopant to form an up-retro well.

REFERENCES:
patent: 4963973 (1990-10-01), Watanabe et al.
patent: 5132235 (1992-07-01), Williams et al.
patent: 5326710 (1994-07-01), Joyce et al.
Acc. No. NB920627 IBM Technical Disclosure Bullentin vol. 35 No. 1B pp 27-28, (Jun. 1992).
Claudio Contiero et al., “Characteristics and Applications of a 0.6 μm Bipolar-CMOS-DMOS Technology combining VLSI Non-Volatile Memories,”IEDM, pp. 465-468 (1996).
Yusuke Kawaguchi et al., “A low on-resistance 60 V MOSFET high side switch and a 30 V npn transistor based on 5 V BiCMOS process,”BCTM, pp. 151-154 (1997).
Young Qiang Li et al., “Integration of High Voltage NMOS Devices into a Submicron BiCMOS Process Using Simple Structural Changes,”IEDM, pp. 403-406 (1994).
Zahir Parpia et al., “A CMOS-Compatible High-Voltage IC Process,”TED, 35(10):1687-1694.
Chin-Yu Tsai et al., “16-60V Rated LDMOS Show Advanced Performance in an 0.72 μm Evolution BiCMOS Power Technology,”IEDM, pp. 367-370 (1997).
Paul G. Y. Tsui, “Integration of Power LDMOS into a Low-Voltage 0.5 μm BiCMOS Technology,”IEDM, pp. 27-30 (1992).
Stanley Wolf, “Silicon Processing for the Vlsi Era”, vol. II, pp. 384-385 and pp. 389-392, Lattice Press, Sunset Beach, CA (1990).

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