High voltage lateral DMOS device with enhanced drift region

Details High voltage lateral DMOS device with enhanced drift region High voltage lateral DMOS device with enhanced drift region

1995-02-06

1996-05-14

Jackson, Jr., Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257401, 257492, H01L 2978

Patent

active

055170463

ABSTRACT:
A lateral DMOS transistor structure formed in N-type silicon is disclosed which incorporates a special N-type enhanced drift region. In one embodiment, a cellular transistor with a polysilicon gate mesh is formed over an N epitaxial layer with P body regions, P.sup.+ body contact regions, N.sup.+ source and drain regions, and N enhanced drift regions. The N enhanced drift regions are more highly doped than the epitaxial layer and extend between the drain regions and the gate. Metal strips are used to contact the rows of source and drain regions. The N enhanced drift regions serve to significantly reduce on-resistance without significantly reducing breakdown voltage.

REFERENCES:
patent: 4922327 (1990-05-01), Mena et al.
patent: 5355008 (1994-10-01), Moyer et al.
patent: 5406110 (1995-04-01), Kwon et al.
patent: 5412239 (1995-05-01), Williams
Taylor Efland, et al., "Optimized Complementary 40V Power LDMOS-FETs Use Existing Fabrication Steps In Submicron CMOS Technology," IEDM, Dec. 1994, pp. 399-402.

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