Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-09-24
2001-03-13
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S275000, C438S299000, C438S277000, C438S286000, C438S585000, C438S595000, C438S981000
Reexamination Certificate
active
06200843
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor devices. In particular, the present invention relates to field effect transistors (FETs) and particular FET structures especially suited for high voltage applications.
BACKGROUND OF THE INVENTION
In mixed voltage applications, often, an input/output (I/O) driver may need to be able to drive and receive voltages above a maximum chip operating voltage. For example, a 1.5 volt technology driver may need to drive and receive 3.3 volts. Since 3.3 volts is too high to be applied to 1.5 V I/O FETs directly, semiconductor chips that include the I/Os and the FETs typically utilize additional circuitry, device, and/or process solutions to avoid high-voltage stress across terminals of the FETs, and especially the thin gate oxide of the FETs.
One example of such solutions includes employing two types of FETs that have different gate oxide thicknesses. According to such a solution, one of the FETs is a “normal” FET, such as an NFET or a PFET, that includes thin oxide for low voltage applications. The other FET includes a thicker gate oxide such that the FETs can withstand a much higher voltage across the oxide.
FIG. 1
illustrates a schematic of a mixed voltage driver and receiver.
Compared to a mixed voltage driver utilizing normal FETs, the thick oxide driver has a much denser layout. However, thick oxide devices have some disadvantages. For example, they have sub-optimal current drive capability due to high equivalent thick gate oxide and inherent higher threshold voltages. To obtain reasonable performances, the FETs typically need to be made large.
FIGS. 1
a
and
1
b
represent schematic diagrams of a known mixed voltage driver and receiver, respectively. These two device structures both suffer from the above-described problems. A thin oxide mixed voltage driver is disclosed in U.S. patent application Ser. No. 08/905,983, filed Aug. 5, 1997, for “Decoupling Scheme For Mixed-Voltage Integrated Circuits”, to E. J. Nowak and M. H. Tong, assigned to the assignee of the present application, the entire disclosure of which is hereby incorporated by reference.
SUMMARY OF THE INVENTION
Aspects of the present invention provide a method for forming a semiconductor device. According to the method, a substrate is provided. A first electrically insulating layer is formed on the substrate. Then, a second electrically insulating layer is formed on the first electrically insulating layer. Next, openings are formed through the second electrically insulating layer down to the level of the first electrically insulating layer. Spacers are formed on opposing sidewalls of the openings. Subsequently, the spacers on one of the opposing side walls of the openings are removed, thereby exposing portions of the first electrically insulating layer. Exposed portions of the first electrically insulating layer in the openings are removed, thereby exposing portions of the substrate. The spacers on another of the opposing sidewalls of the openings are removed, thereby exposing portions of the first electrically insulating layer. A third electrically insulating layer is formed in the openings over the exposed portions of the first electrically insulating layer and the exposed portions of the substrate.
Other aspects of the present invention provide a semiconductor device. The semiconductor device includes a substantially planar substrate including a plurality of source regions. Also, the device includes a plurality of drain regions, one associated with one of the source regions. Each of the source regions is separated from the associated drain region by an associated substrate region. A plurality of regions of a dielectric material are arranged on the substrate. Each region of dielectric material overlaps one of the source regions, one of the associated drain regions, and one of the associate substrate regions. Each of the plurality of regions of dielectric material is thicker over the underlying drain region that over the underlying source region. The device also includes a plurality of gate conductor regions, one formed on each of the plurality of regions of dielectric material. An inside edge of the thicker portion of each region of dielectric material is self-aligned to an outside edge.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described only the preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.
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Bryant Andres
Nowak Edward J.
Tong Minh H.
Hoang Quoc
International Business Machines - Corporation
Nelms David
Pollock Vande Sande & Amernick
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