High voltage field effect transistors with selective gate deplet

Details High voltage field effect transistors with selective gate deplet High voltage field effect transistors with selective gate deplet

1998-01-28

2000-04-25

Fahmy, Wael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438276, 257204, H01L 218234, H01L 218236

Patent

active

06054354&

ABSTRACT:
A method of forming field effect transistors (FETS) on a silicon wafer. A gate layer, polysilicon, is formed on a gate dielectric layer (oxide) on the silicon wafer. High voltage device locations are defined and blocked while normal NFETs and PFETs are formed. If the FET process is a gate predope process, the gate layer is blocked during predoping and patterned after the predoping is complete. Otherwise, the gate layer is patterned prior to doping. After gate definition, high voltage FETs are unblocked and implanted with a dopant, preferably boron (B) or (P), which dopes gates and source/drain regions such that they are depleted, resulting in a thicker effective gate dielectric than normal NFETs and PFETs.

REFERENCES:
patent: 5254487 (1993-10-01), Tamagawa
patent: 5296401 (1994-03-01), Mitsui et al.
patent: 5449637 (1995-09-01), Saito et al.
patent: 5468666 (1995-11-01), Chapman
patent: 5480828 (1996-01-01), Hsu et al.
patent: 5698458 (1997-12-01), Hsue et al.
patent: 5712201 (1998-01-01), Lee et al.
English language abstract of Japanese Patent number 61-179577

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