Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-01-13
2001-07-10
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S306000
Reexamination Certificate
active
06258674
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a high voltage field effect transistor and a method of fabricating the same. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for increasing a secondary breakdown voltage.
2. Discussion of the Related Art
Power MOSFETs have a high switching speed comparing to the other power devices. Specifically, high voltage lateral power MOSFETs have been preferred as large-integrated power devices in recent years since an ON resistance is low in a device of less than 300 V having a relatively low internal pressure.
For example, the high voltage power device includes DMOSFET (Double-diffused MOSFET), IGBT (Insulated Gate Bipolar Transistor), EDMOSFET (Extended Drain MOSFET), and LDMOSFET (Lateral Double-Diffused MOSFET).
Among these devices, LDMOSFETs are widely used for HSD (High Side Driver) and LSD (Low Side Driver), or H-bridge circuits. Although the LDMOSFETs are easy to fabricate, a threshold voltage becomes high because a dopant concentration of the channel region, which determines the structure of the LDMOSFET, is not uniform. Thus, a breakdown at the surface of the silicon substrate occurs in a drift region neighboring the channel. Accordingly, the EDMOSFET has been recently developed to overcome the above-mentioned disadvantages.
An EDMOSFET according to a background art will be described wit h reference to the attached drawings.
FIGS. 1 and 2
are cross-sectional views illustrating an n-channel EDMOSFET and a p-channel EDMOSFET according to the background art.
Initially referring to
FIG. 1
, a structure of the n-channel EDMOSFET according to the background art includes a p-type drift region
2
and an n-type drift region
3
respectively formed in a p-type well
1
. The n-type drift region
3
has a lightly doped drain (LDD) region in the vicinity of a gate to form a channel. On the p-type well
1
having the p-type drift region
2
and the n-type drift region
3
, a gate electrode
4
is formed to have a gate insulating layer
32
interposed therebetween. One side edge of the gate electrode
4
is positioned at the boundary between the p-type drift region
2
and the n-type drift region
3
.
In the p-type drift region
2
, a heavily doped n-type source region
3
is formed around one side of the gate electrode
4
, while a heavily doped p-type impurity region
6
for an electrical contact is at one side of the source region
5
. A heavily doped n-type drain region
7
is spaced apart at a predetermined distance from the gate electrode
4
in the n-type drift region
3
.
A source electrode
8
is disposed on the heavily doped n-type source region
5
including the heavily doped p-type impurity region
6
. A drain electrode
9
is formed on the heavily doped n-type drain region
7
, while a field plate
10
is formed over the one side edge of the gate electrode
4
and the n-type drift region
3
.
On the other hand, a p-channel EDMOSFET according to the background art has a similar structure to the n-channel EDMOSFET except for conductivity types. As shown in
FIG. 2
, an n-type drift region
12
and a p-type drift region
13
are formed in an n-type well
11
. The p-type drift region
13
has an LDD in the vicinity of a gate to form a channel. On the n-type well
11
having the n-type drift region
12
and the p-type drift region
13
, a gate electrode
14
is formed to have a gate insulating layer
32
interposed therebetween. One side edge of the gate electrode
14
is positioned at the boundary between the n-type drift region
12
and the p-type drift region
13
.
In the n-type drift region
12
, a heavily doped p-type source region
15
is formed around one side of the gate electrode
14
and a heavily doped n-type impurity region
16
for a body contact is around one side of the source region
15
. A heavily doped p-type drain region
17
is spaced apart at a predetermined distance from the gate electrode
14
in the p-type drift region
13
.
A source electrode
18
is disposed on the heavily doped p-type source region
15
including the heavily doped n-type impurity region
16
. A drain electrode
19
is formed on the heavily doped p-type drain region
17
, while a field plate
20
is over the one side edge of the gate electrode
14
and the p-type drift region
13
.
The operation of such a EDMOSFET according to the background art will be described as follows.
Since the operation of the n-channel EDMOSFET is the same as that of the p-type channel EDMOSFET, only the former will be described for example.
Upon applying a voltage higher than a threshold voltage to the gate electrode
4
and a voltage higher than the voltage of the source electrode
8
to the drain electrode
9
, the voltage flows to the drain region
7
through the n-type drift region
3
through the channel region below the gate electrode
4
from the source region
5
. At this stage, the breakdown voltage is increased because the field plate
10
prevents a breakdown at the end portion of the gate neighboring the drain region
8
. Furthermore, when an appropriate voltage is applied to the field plate
10
, a current path of the drift regions will be adjusted, thereby reducing a conduction resistance.
The MOSFET can be operated by two different methods. One method is to apply a gate voltage to the field plate
10
to raise the breakdown voltage and simultaneously to employ characteristics of the conduction resistance. The other is to reduce the conduction resistance by applying a constant voltage to the field plate spaced apart from the gate electrode.
However, the aforementioned EDMOSFET and LDMOSFET according to the background art have the following problems.
Although the EDMOSFET and LDMOSFET according to the background art is designed to have a primary breakdown voltage ‘high’ without applying a voltage to the gate electrode, a secondary breakdown voltage is decreased when a voltage is applied to the gate electrode. Accordingly, the EDMOSFET or LDMOSFET according to the background art, which is designed to have the primary breakdown voltage as high as about 170 V, has the secondary breakdown voltage not higher than about 60 V when 20 V is applied to the gate electrode.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a high-voltage field effect transistor and method of fabricating the same that substantially obviates one or more of problems due to limitations and disadvantages of the related art.
An objective of the present invention is to provide a high voltage field effect transistor with enhanced SOA (Safe Operation Area) characteristic by improving a secondary breakdown voltage, and its fabricating method.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a high voltage field effect transistor includes a first conductivity type drift region and a second conductivity type drift region formed within a first conductivity type well, a gate electrode formed on the first conductivity type well, a heavily doped second conductivity type source region and a heavily doped first conductivity type impurity region formed in the first conductivity type drift region on the one side of the gate electrode, a heavily doped second conductivity type drain region formed in the second conductivity type drift region and spaced at a predetermined distance from the gate electrode, a lightly doped second conductivity type buffer layer formed in the second conductivity type drift region to surround the heavily doped second conducti
Kwon Oh Kyong
Lee Mueng Ryul
Coleman William David
LG Semicon Co. Ltd.
Morgan & Lewis & Bockius, LLP
Pham Long
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